C8051F121-GQR Silicon Laboratories Inc, C8051F121-GQR Datasheet - Page 269
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C8051F121-GQR
Manufacturer Part Number
C8051F121-GQR
Description
IC 8051 MCU FLASH 128K 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F121-GQR
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F121-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
- Current page: 269 of 350
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19.4.5. Status Register
The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus0 inter-
face. There are 28 possible SMBus0 states, each with a corresponding unique status code. The five most
significant bits of the status code vary while the three least-significant bits of a valid status code are fixed at
zero when SI = ‘1’. Therefore, all possible status codes are multiples of eight. This facilitates the use of sta-
tus codes in software as an index used to branch to appropriate service routines (allowing 8 bytes of code
to service the state or jump to a more extensive service routine).
For the purposes of user software, the contents of the SMB0STA register is only defined when the SI flag is
logic 1. Software should never write to the SMB0STA register; doing so will yield indeterminate results. The
28 SMBus0 states, along with their corresponding status codes, are given in Table 1.1.
Bits7–1: SLV6–SLV0: SMBus0 Slave Address.
Bit0:
Bits7–3: STA7–STA3: SMBus0 Status Code.
Bits2–0: STA2–STA0: The three least significant bits of SMB0STA are always read as logic 0 when
STA7
SLV6
R/W
R/W
Bit7
Bit7
These bits are loaded with the 7-bit slave address to which SMBus0 will respond when oper-
ating as a slave transmitter or slave receiver. SLV6 is the most significant bit of the address
and corresponds to the first bit of the address byte received.
GC: General Call Address Enable.
This bit is used to enable general call address (0x00) recognition.
0: General call address is ignored.
1: General call address is recognized.
These bits contain the SMBus0 Status Code. There are 28 possible status codes; each sta-
tus code corresponds to a single SMBus state. A valid status code is present in SMB0STA
when the SI flag (SMB0CN.3) is set to logic 1. The content of SMB0STA is not defined when
the SI flag is logic 0. Writing to the SMB0STA register at any time will yield indeterminate
results.
the SI flag is logic 1.
STA6
SLV5
R/W
R/W
Bit6
Bit6
SFR Definition 19.4. SMB0ADR: SMBus0 Address
SFR Definition 19.5. SMB0STA: SMBus0 Status
SLV4
STA5
R/W
R/W
Bit5
Bit5
SLV3
STA4
R/W
R/W
Bit4
Bit4
Rev. 1.4
SLV2
STA3
R/W
R/W
Bit3
Bit3
C8051F120/1/2/3/4/5/6/7
STA2
SLV1
R/W
R/W
Bit2
Bit2
C8051F130/1/2/3
STA1
SLV0
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Page:
SFR Address:
SFR Page:
STA0
R/W
GC
R/W
Bit0
Bit0
0xC3
0
0xC1
0
00000000
Reset Value
Reset Value
11111000
269
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