DSP56F805FV80E Freescale Semiconductor, DSP56F805FV80E Datasheet - Page 32

• Manufacturer Part Number: DSP56F805FV80E
• Description: IC DSP 80MHZ 31.5K FLASH 144LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxr

Specifications of DSP56F805FV80E

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 71KB (35.5K x 16)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Product: DSPs
• Data Bus Width: 16 bit
• Processor Series: DSP56F8xx
• Core: 56800
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: MAC
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 32
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: PBMCUSLK, DSP56F800DEMO-E
• Interface Type: SCI, SPI
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.6 External Bus Asynchronous Timing
32
Address Valid to WR Asserted
WR Width Asserted
Wait states = 0
Wait states > 0
WR Asserted to D0–D15 Out Valid
Data Out Hold Time from WR Deasserted
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
RD Deasserted to Address Not Valid
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
Input Data Hold to RD Deasserted
RD Assertion Width
Wait states = 0
Wait states > 0
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
Address Valid to RD Asserted
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
WR Deasserted to RD Asserted
RD Deasserted to RD Asserted
WR Deasserted to WR Asserted
RD Deasserted to WR Asserted
Operating Conditions:
Characteristic
Table 3-10 External Bus Asynchronous Timing
V
SS
= V
SSA
= 0 V, V
56F805 Technical Data, Rev. 16
DD
= V
Symbol
t
t
t
t
t
t
WRWR
t
WRRD
RDWR
t
t
t
t
ARDD
t
ARDA
t
RDRD
AWR
t
WRD
DOH
DOS
RDA
DRD
t
RDD
t
DDA
WR
RD
AD
= 3.0–3.6 V, T
(T*WS) + 18.7
(T*WS)+7.5
(T*WS)+6.4
(T*WS)+19
18.7
14.1
12.8
Min
-4.4
A
6.5
7.5
4.8
2.2
6.8
19
—
—
—
—
—
0
0
0
= –40° to +85°C, C
1, 2
(T*WS) + 2.4
(T*WS)+1
L
T + 4.2
≤
Max
2.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
1
50pF, f
op
= 80MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns