R5F64185DFD#U0 Renesas Electronics America, R5F64185DFD#U0 Datasheet - Page 26

• Manufacturer Part Number: R5F64185DFD#U0
• Description: MCU 384+8KB FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C/R32C/100/118r

Specifications of R5F64185DFD#U0

• Core Processor: R32C/100
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 120
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R32C/118 Group
REJ03B0255-0110
Jun 23, 2010
2.1.8.5
2.1.8.6
2.1.8.7
2.1.8.8
2.1.8.9
2.1.8.10
2.1.8.11
2.1.8.12
2.1.8.13
2.1.8.14
This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the
register bank 1 is selected.
This flag becomes 1 if an overflow occurs in an operation; otherwise it is 0.
This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable
them, set this flag to 1. When an interrupt is accepted, the flag becomes 0.
To select the interrupt stack pointer (ISP), set this flag to 0. To select the user stack pointer (USP), set
this flag to 1.
It becomes 0 when a hardware interrupts is accepted or when an INT instruction designated by a
software interrupt number from 0 to 127 is executed.
This flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand has invalid numbers (subnormal numbers).
This flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand has invalid numbers (subnormal numbers).
The processor interrupt priority level (IPL), consisting of three bits, selects a processor interrupt priority
level from level 0 to 7. An interrupt is acceptable when the interrupt request level is higher than the
selected IPL.
When the processor interrupt priority level (IPL) is set to 111b (level 7), all interrupts are disabled.
This bit designates the radix point. It also specifies which portion of the fixed-point multiplication result
to take. It is used in the MULX instruction.
The 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results.
Only set this bit to 0. The read value is undefined.
Register Bank Select Flag (B flag)
Overflow Flag (O flag)
Interrupt Enable Flag (I flag)
Stack Pointer Select Flag (U flag)
Floating-point Underflow Flag (FU flag)
Floating-point Overflow Flag (FO flag)
Processor Interrupt Priority Level (IPL)
Fixed-point Radix Point Designation Bit (DP bit)
Floating-point Rounding Mode (RND)
Reserved
Rev.1.10
2. Central Processing Unit (CPU)
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