R5F64169DFD#U0 Renesas Electronics America, R5F64169DFD#U0 Datasheet - Page 20

• Manufacturer Part Number: R5F64169DFD#U0
• Description: MCU 1MB+8KB FLASH 63K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C/R32C/100/116r

Specifications of R5F64169DFD#U0

• Core Processor: R32C/100
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 120
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 63K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R32C/116 Group
REJ03B0253-0110
Jun 23, 2010
Table 1.15
Note:
Bus control pins
1.
Function
Pins BC2 /D1, WR2 , WR3 , BC2 , and BC3 are available in the 144-pin package only.
Pin Definitions and Functions (2/4)
Rev.1.10
BC0 /D0, BC2
(1)
CS0 to CS3
WR0 / WR1 / WR2 /
WR3
WR / BC0 / BC1 /
BC2 / BC3
RD
ALE
HOLD
HLDA
RDY
(1)
Symbol
/
D1
I/O
I/O
O
O
O
O
I
I
Output of byte control ( BC0 and BC2 ) and input/output of
data (D0 and D1) by time-division while accessing an
external memory space with multiplexed bus
Chip select output
Output of write, byte control, and read signals. Either WRx
or WR and BCx can be selected by a program.
Data is read when RD is low.
Latch enable signal in multiplexed bus format
The MCU is in a hold state while this pin is held low
This pin is driven low while the MCU is held in a hold state
Bus cycle is extended by the CPU if this pin is low on the
falling edge of the BCLK
• When WR0 , WR1 , WR2 , WR3 , and RD are selected,
• When WR , BC0 , BC1 , BC2 , BC3 , and RD are selected,
data is written to the following address:
or
data is written, when WR is low
and
the following address is accessed:
or
4n+0, when WR0 is low
4n+1, when WR1 is low
4n+2, when WR2 is low
4n+3, when WR3 is low
on 32-bit external data bus
an even address, when WR0 is low
an odd address, when WR1 is low
on 16-bit external data bus
4n+0, when BC0 is low
4n+1, when BC1 is low
4n+2, when BC2 is low
4n+3, when BC3 is low
on 32-bit external data bus
an even address, when BC0 is low
an odd address, when BC1 is low
on 16-bit external data bus
Description
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