MCF5272CVM66J Freescale Semiconductor, MCF5272CVM66J Datasheet - Page 523

• Manufacturer Part Number: MCF5272CVM66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Cpu Speed: 66MHz
• Embedded Interface Type: EMI, ETHERNET, I2C, SPI, UART, USB
• Digital Ic Case Style: MAPBGA
• No. Of Pins: 196
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
0x020C
0x022C
0x024C
0x026C
0x028C
0x0180
0x0184
0x0200
0x0204
0x0208
0x0210
0x0220
0x0224
0x0228
0x0230
0x0240
0x0244
0x0248
0x0250
0x0260
0x0264
0x0268
0x0270
0x0280
0x0284
0x0288
MBAR
Offset
MBAR
Offset
Watchdog Interrupt Reference Register (WIRR)
Watchdog Reset Reference Register (WRRR)
[31:24]
[31:24]
Timer 0 Reference Register (TRR0)
Timer 1 Reference Register (TRR1)
Timer 2 Reference Register (TRR2)
Timer 3 Reference Register (TRR3)
Watchdog Counter Register (WCR)
Timer 0 Capture Register (TCAP0)
Timer 1 Capture Register (TCAP1)
Timer 2 Capture Register (TCAP2)
Timer 3 Capture Register (TCAP3)
Timer 0 Counter Register (TCN0)
Timer 1 Counter Register (TCN1)
Timer 2 Counter Register (TCN2)
Timer 3 Counter Register (TCN3)
Watchdog Event Register (WER)
Timer 0 Mode Register (TMR0)
Timer 1 Mode Register (TMR1)
Timer 2 Mode Register (TMR2)
Timer 3 Mode Register (TMR3)
Timer 0 Event Register (TER0)
Timer 1 Event Register (TER1)
Timer 2 Event Register (TER2)
Timer 3 Event Register (TER3)
MCF5272 ColdFire
Reserved
Reserved
Table A-12. SDRAM Controller Memory Map
Table A-13. Timer Module Memory Map
®
Integrated Microprocessor User’s Manual, Rev. 3
[23:16]
[23:16]
SDRAM Configuration Register (SDCR)
[15:8]
[15:8]
SDRAM Timing Register (SDTR)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
List of Memory Maps
[7:0]
[7:0]
A-7