MCF5272CVM66J Freescale Semiconductor, MCF5272CVM66J Datasheet - Page 86
MCF5272CVM66J
Manufacturer Part Number
MCF5272CVM66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Cpu Speed
66MHz
Embedded Interface Type
EMI, ETHERNET, I2C, SPI, UART, USB
Digital Ic Case Style
MAPBGA
No. Of Pins
196
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVM66J
Manufacturer:
NSC
Quantity:
36
Company:
Part Number:
MCF5272CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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ColdFire Core
Table 2-8
1
2-18
CPUSHL
HALT
MOVE from SR
MOVE to SR
MOVEC
RTE
STOP
WDEBUG
1
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TRAP
TRAPF
TST
UNLK
WDDATA
Instruction
The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE].
By default the HALT instruction is a supervisor-mode instruction; however, it can be configured to allow user-mode execution
by setting CSR[UHE].
Instruction
1
describes supervisor-mode instructions.
<ea>y,Dx
Dy,<ea>x
<ea>y,Ax
#<data>,Dx
#<data>,<ea>x
Dy,Dx
Dx
#<vector>
None
#<data>
<ea>y
Ax
<ea>y
Operand Syntax
(bc),(Ax)
none
SR, Dx
Dy,SR
#<data>,SR
Ry,Rc
None
#<data>
<ea-2>y
Operand Syntax
MCF5272 ColdFire
Table 2-7. User-Mode Instruction Set Summary (continued)
Table 2-8. Supervisor-Mode Instruction Set Summary
.L
.L
.L
.L
.L
.L
.W
Unsized
Unsized
.W
.L
.B,.W,.L
Unsized
.B,.W,.L
Unsized
Unsized
.W
.W
.L
Unsized
.W
.L
Operand Size
Operand Size
®
Integrated Microprocessor User’s Manual, Rev. 3
Invalidate instruction cache line
Enter halted state
SR → Dx
Source → SR
Ry → Rc
Rc
0x002
0x004
0x005
0x801
0xC00
0xC04
0xC0F
(SP+2) → SR; SP+4 → SP; (SP) → PC; SP + formatfield ⎯ SP
Immediate data → SR; enter stopped state
<ea-2>y → debug module
Destination – source → destination
Destination – source → destination
Destination – immediate data → destination
Destination – immediate data → destination
Destination – source – X → destination
MSW of Dx ←→ LSW of Dx
SP – 4 → SP;PC → (SP);
SP – 2 → SP;SR → (SP);
SP – 2 → SP; format → (SP);
Vector address → PC
PC + 2 → PC
PC + 4 → PC
PC + 6 → PC
Set condition codes
Ax →SP; (SP) → Ax; SP + 4 → SP
<ea>y →DDATA port
Register Definition
Cache control register (CACR)
Access control register 0 (ACR0)
Access control register 1 (ACR1)
Vector base register (VBR)
ROM base address register (ROMBAR)
RAM base address register (RAMBAR)
Module base address register (MBAR)
Operation
Operation
Freescale Semiconductor
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