HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 254

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

End Address Register (EDAR)
EDAR is an 8-bit read/write register, for designating a transfer end address in the address space
(H'FF80 to H'FF9F) allocated to the 32-byte data buffer. The lower 5 bits of EDAR correspond to
the lower 5 bits of the address. The extent of continuous data transfer is defined in STAR and in
EDAR. If the same value is designated by STAR and EDAR, only 1 byte of data is transferred.
Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified.
Upon reset, EDAR is initialized to H'E0.
Serial Control Register 2 (SCR2)
SCR2 is an 8-bit read/write register for selecting the serial clock, and for setting the gap inserted
between data during continuous transfer when SCI2 uses an internal clock.
Upon reset, SCR2 is initialized to H'E0.
Bits 7 to 5—Reserved Bits: Bits 7 to 5 are reserved; they are always read as 1, and cannot be
modified.
Bits 4 and 3—Gap Select 1, 0 (GAP1 to GAP0): When SCI2 uses an internal clock, gaps can be
inserted between successive data bytes. Bits 4 and 3 designate the length of these gaps. During a
gap, pin SCK
level.
Bit 4: GAP1
0
1
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
2
remains at the high level. When no gap is inserted, the STRB signal stays at the low
Bit 3: GAP0
0
1
0
1
—
—
—
—
7
1
7
1
—
—
—
—
6
1
6
1
Description
No gaps between bytes
A gap of 8 clock cycles is inserted between bytes
A gap of 24 clock cycles is inserted between bytes
A gap of 56 clock cycles is inserted between bytes
—
—
—
—
5
1
5
1
EDA4
GAP1
R/W
R/W
4
0
4
0
EDA3
GAP0
R/W
R/W
3
0
3
0
EDA2
CKS2
R/W
R/W
2
0
2
0
EDA1
CKS1
R/W
R/W
1
0
1
0
(initial value)
EDA0
CKS0
R/W
R/W
0
0
0
0
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