M30878FJAGP#U5 Renesas Electronics America, M30878FJAGP#U5 Datasheet - Page 398
M30878FJAGP#U5
Manufacturer Part Number
M30878FJAGP#U5
Description
IC M32C/87 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M30878FJAGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30878FJAGP#U5M30878FJAGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 374 of 587
Figure 22.42
Group i SI/O Expansion Receive Control Register (i=0,1)
b7 b6 b5 b4
0
NOTES:
1. The GiERC register is used in HDLC data processing mode.
2. When the ACRC bit in the GiEMR register is set to 1 (CRC initialized), set the CMP3E bit to 1.
Set the GiERC register to 0010 0000b in clock synchronous mode, set it to 00h in UART mode.
b3
G0ERC, G1ERC Registers
b2
b1
b0
Bit Symbol
RCRCE
CMP0E
CMP1E
CMP2E
CMP3E
RSHTE
RBSF1
(b6)
Symbol
G0ERC
G1ERC
−
Data compare function 0
select bit
Data compare function 1
select bit
Data compare function 2
select bit
Data compare function 3
select bit
Receive CRC enable bit
Receive shift operation
enable bit
Reserved bit
Receive bit stuffing
"0" delete select bit
Bit Name
Address
00FDh
013Dh
0 : The GiDR register (receive data register)
0 : The GiDR register (receive data register)
1 : The GiDR register is compared with the
0 : The GiDR register (receive data register)
1 : The GiDR register is compared with the
0 : The GiDR register (receive data register)
1 : The GiDR register is compared with the
1 : The GiDR register is compared with the
0 : Not used
1 : Used
0 : Receive shift operation disabled
1 : Receive shift operation enabled
Set to 0
0 : "0" is not deleted
1 : "0" is deleted
is not compared with the GiCMP3 register
is not compared with the GiCMP0 register
GiCMP0 register
is not compared with the GiCMP1 register
GiCMP1 register
is not compared with the GiCMP2 register
GiCMP2 register
GiCMP3 register
Function
(2)
(1)
After Reset
00h
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
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