M30878FJAGP#U5 Renesas Electronics America, M30878FJAGP#U5 Datasheet - Page 408
M30878FJAGP#U5
Manufacturer Part Number
M30878FJAGP#U5
Description
IC M32C/87 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M30878FJAGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30878FJAGP#U5M30878FJAGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 384 of 587
Figure 22.50
(2) When the Serial Clock is Generated in Channel 3 Phase-Delayed Waveform Output Mode (Group 1)
(1) When f8, f2n or External Clock is Selected as the Serial Clock (Groups 0 and 1)
Output from ISTXDi pin
(Transmit data)
Output from ISCLK1 pin
(Serial clock in the
channel 3 generation
function)
(Receive data)
Output from ISTXD1 pin
Input to ISRXD1 pin
Input to ISRXDi pin
i = 0, 1; j = 1, 3; k = 0, 2
The above applies under the following conditions:
- Bits CCS1 and CCS0 or bits CCS3 and CCS2 in the CCS register are set to 10b or 11b
- The UFORM bit in the GiMR register is set to 0 (LSB first)
- Bits IPOL and OPOL in the GiCR register are set to 0 (not inverted)
NOTES:
n: Setting value of the G1PO0 register
m: Setting value of the G1PO3 register
The above applies under the following conditions:
- In the G1MR register, the CKDIR bit is set to 0 (internal clock), the UFORM bit is set to 0 (LSB first)
- Bits CCS3 and CCS2 in the CCS register are set to 00b (Clock generated with waveform generation function)
- Bits IPOL and OPOL in the G1CR register are set to 0 (not inverted)
NOTE:
SIO1RR bit in the
SIO1TR bit in the
SIOiRR bit in the
SIOiTR bit in the
SIOiTR bit in the
IIO3IR register
IIOjIR register
1. This applies when IRS bit in the GiMR register is set to 0 (No data in the GiTB register).
2. This applies when IRS bit in the GiMR register is set to 1 (Transmit operation completed).
1. This applies when the IRS bit in the G1MR register is set to 0 (No data in the G1TB register).
IIOjIR register
(Transmit data)
Serial clock
(Receive data)
IIOkIR register
IIO2IR register
GiCR register
Base Timer
TE Bit in the
Transmit and Receive Operation in Clock Synchronous Mode (Groups 0 and 1)
(1)
(2)
(1)
n + 2
Write to the GiTB register
"H"
"H"
"L"
"L"
m
1
0
1
0
1
0
1
0
1
0
1
0
G1TB register
Write to the
Set to 0 by a program
Set to 0 by a program
Bit 0
Bit 0
Bit 0
Bit 0
The base timer is reset by the channel 0
waveform generation function
Bit 1
Bit 1
Bit 1
Bit 1
Bit 2
Bit 2
Bit 2
Bit 2
Bit 6
Bit 6
Bit 6
Bit 6
Set to 0 by a program
Bit 7
Bit 7
Bit 7
Bit 7
Set to 0 by a program
Set to 0 by a program
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