M30620FCAFP#D3 Renesas Electronics America, M30620FCAFP#D3 Datasheet - Page 195
![IC M16C MCU FLASH 128K 100LQFP](/photos/28/61/286112/100-bqfp__prqp0100jb-a_sml.jpg)
M30620FCAFP#D3
Manufacturer Part Number
M30620FCAFP#D3
Description
IC M16C MCU FLASH 128K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30620FCAFP#D3
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Timing (Vcc = 3V)
192
Switching characteristics (referenced to V
Table 1.23.37. Memory expansion and microprocessor modes (with no wait)
Figure 1.23.7. Port P0 to P10 measurement circuit
Note 1: Calculated according to the BCLK frequency as follows:
Note 2: This is standard value shows the timing when the output is off,
Note 3: Specify a product of -40°C to 85°C to use it.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
d(BCLK-CS)
h(BCLK-CS)
d(BCLK-ALE)
h(BCLK-ALE)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
h(WR-AD)
d(BCLK-RD)
h(BCLK-RD)
d(DB-WR)
h(WR-DB)
Symbol
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
by a circuit of the right figure.
For example, when V
of output “L” level is
td(DB – WR) =
Address output hold time (WR standard)
RD signal output delay time
WR signal output delay time
Address output hold time (BCLK standard)
ALE signal output delay time
RD signal output hold time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output hold time (WR standard)(Note2)
Address output delay time
Address output hold time (RD standard)
Chip select output delay time
Chip select output hold time (BCLK standard)
ALE signal output hold time
Data output delay time (WR standard)
t = –CR X ln (1 – V
t = – 30pF X 1k
= 6.7ns.
f(BCLK) X 2
Parameter
85
OL
10
o
= 0.2V
C (Note 3), CM15=“1” unless otherwise specified)
9
X ln (1 – 0.2V
OL
/ V
– 80
CC
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
CC
, C = 30pF, R = 1k , hold time
)
CC
[ns]
CC
= 3V, V
/ V
30pF
CC
)
SS
Measuring condition
Figure 1.23.7
= 0V at Topr = – 20
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(Note1)
Min.
— 4
Standard
4
0
0
4
0
0
4
0
o
C to 85
DBi
Max.
60
60
60
60
60
80
M16C / 62A Group
o
Mitsubishi microcomputers
C / – 40
V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CC
R
C
o
= 3V
C to
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