M30624FGNHP#U5 Renesas Electronics America, M30624FGNHP#U5 Datasheet - Page 146

• Manufacturer Part Number: M30624FGNHP#U5
• Description: MCU 3V 256K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGNHP#U5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UART2 Special Mode Register
Figure 1.17.28. Some other functions added
Some other functions added are explained here. Figure 1.17.28 shows their workings.
Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The
bus collision detect interrupt occurs when the R
mity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”. If
this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0 rather than at
the rising edge of the transfer clock.
Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable
bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus
collision detect interrupt request bit (nonconformity).
Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit
to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal.
1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)
2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)
3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)
CLK
TxD/RxD
Timer A0
With "1: falling edge of RxD
0: In normal state
CLK
TxD/RxD
Bus collision
detect interrupt
request bit
Transmit
enable bit
TxD
CLK
RxD
CLK
TxD
Enabling transmission
0: Rising edges of the transfer clock
2
" selected
X
D
2
level and T
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
X
D
2
level do not match, but the nonconfor-
1: Timer A0 overflow
M16C / 62N Group
Mitsubishi microcomputers
143