UPD78F0500MC-5A4-A Renesas Electronics America, UPD78F0500MC-5A4-A Datasheet - Page 275

• Manufacturer Part Number: UPD78F0500MC-5A4-A
• Description: MCU 8BIT FLASH SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500MC-5A4-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Operation as interval timer
Operation as square-wave output
Operation as external event counter
Operation in the clear & start mode
entered by TI00n pin valid edge input
Operation as free-running timer
Operation as PPG output
Operation as one-shot pulse output
Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output is
Remarks 1. N: CR00n register set value, M: CR01n register set value
(iii) Setting range when CR00n or CR01n is used as a compare register
When CR00n or CR01n is used as a compare register, set it as shown below.
not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the timer
counter (TM0n register) is changed from 0000H to 0001H.
• When the timer counter is cleared due to overflow
• When the timer counter is cleared due to TI00n pin valid edge (when clear & start mode is entered by TI00n
• When the timer counter is cleared due to compare match (when clear & start mode is entered by match
pin valid edge input)
between TM0n and CR00n (CR00n = other than 0000H, CR01n = 0000H))
2. For details of TMC0n3 and TMC0n2, see 7.3 (1) 16-bit timer mode control register 0n (TMC0n).
3. n = 0:
n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products
Operation
78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,
78K0/KD2 products
Compare register set value
Timer operation enable bit
Interrupt request signal
(TMC0n3, TMC0n2)
TM0n register
0000H < N ≤ FFFFH
0000H
M < N ≤ FFFFH
0000H
(0000H)
CR00n Register Setting Range
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Note
Note
≤ N ≤ FFFFH
≤ N ≤ FFFFH (N ≠ M)
disabled (00)
Operation
is not generated
Interrupt signal
Timer counter clear
Operation enabled
(other than 00)
0000H
Normally, this setting is not used. Mask the
match interrupt signal (INTTM01n).
0000H
0000H
0000H
Interrupt signal
is generated
Note
Note
Note
Note
CR01n Register Setting Range
≤ M ≤ FFFFH
≤ M ≤ FFFFH
≤ M < N
≤ M ≤ FFFFH (M ≠ N)
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