UPD78F9222CS-CAC-A Renesas Electronics America, UPD78F9222CS-CAC-A Datasheet - Page 284

• Manufacturer Part Number: UPD78F9222CS-CAC-A
• Description: MCU 8BIT 4KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9222CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.8.2 Cautions on self programming function
18.8.3 Registers used for self programming function
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The following registers are used for the self programming function.
The 78K0S/KA1+ has an area called a protect byte at address 0081H of the flash memory.
(1) Flash programming mode control register (FLPMC)
No instructions can be executed while a self programming command is being executed. Therefore, clear and
restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self
programming. Refer to Table 18-10 for the time taken for the execution of self programming.
Interrupts that occur during self programming can be acknowledged after self programming mode ends. To avoid
this operation, disable interrupt servicing (by setting MK0 and MK1 to FFH, and executing the DI instruction)
before the mode is shifted from the normal mode to the self programming mode by a specific sequence.
RAM is not used while a self programming command is being executed.
If the supply voltage drops or the reset signal is input while the flash memory is being written or erased,
writing/erasing is not guaranteed.
The value of the blank data set during block erasure is FFH.
Set the CPU clock beforehand so that it is 1 MHz or higher during self programming.
Execute self programming after executing the NOP and HALT instructions immediately after executing a specific
sequence to set self programming mode. At this time, the HALT instruction is automatically released after 10 s
(MAX.) + 2 CPU clocks (f
If the clock of the oscillator or an external clock is selected as the system clock, execute the NOP and HALT
instructions immediately after executing a specific sequence to set self programming mode, wait for 8 s after
releasing the HALT status, and then execute self programming.
Check FPRERR using a 1-bit memory manipulation instruction.
The state of the pins in self programming mode is the same as that in HALT mode.
Since the security function set via on-board/off-board programming is disabled in self programming mode, the
self programming command can be executed regardless of the security function setting. To disable write or erase
processing during self programming, set the protect byte.
Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register
(FLAPHC) to 0 before executing the self programming command. If the self programming command is executed
with these bits set to 1, the device may malfunction.
Clear the value of the FLCMD register to 00H immediately before setting to self programming mode and normal
mode.
Flash programming mode control register (FLPMC)
Flash protect command register (PFCMD)
Flash status register (PFS)
Flash programming command register (FLCMD)
Flash address pointers H and L (FLAPH and FLAPL)
Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and FLAPLC)
Flash write buffer register (FLW)
This register is used to set the operation mode when data is written to the flash memory in the self
Data can be written to FLPMC only in a specific sequence (refer to 18.8.3 (2) Flash protect command
programming mode, and to read the set value of the protect byte.
register (PFCMD)) so that the application system does not stop by accident because of malfunctions due to
noise or program hang-ups.
CPU
).
CHAPTER 18 FLASH MEMORY
User’s Manual U16898EJ6V0UD