UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 664
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UPD78F1203MC-CAB-AX
Manufacturer Part Number
UPD78F1203MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1203MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
RENESAS
Quantity:
15 000
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
NEC
Quantity:
20 000
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(2) Operation procedure
Caution
Figure 13-41. Initial Setting Procedure for Master Transmission/Reception
After setting the SAU0EN bit of peripheral enable register 0 (PER0) to 1, be sure to set
serial clock select register 0 (SPS0) after 4 or more f
Changing setting of SOE0 register
Starting communication
Setting SMR0n register
Setting SCR0n register
Setting SDR0n register
Writing to SS0 register
Setting PER0 register
Setting SPS0 register
Starting initial setting
Setting SO0 register
Setting port
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U19678EJ1V1UD
Set the initial output level of the serial
clock (CKO0n) and serial data (SO0n).
Enable data output and clock output of
the target channel by setting a port
register and a port mode register.
Set the SS0n bit of the target channel to 1
and set SE0n bit to 1 (to enable operation).
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the
transfer clock by dividing the operation
clock (f
Set the SOE0n bit to 1 and enable data
output of the target channel.
Set transmit data to the SIOp register (bits
7 to 0 of the SDR0n register) and start
communication.
MCK
)).
CLK
clocks have elapsed.
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