UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 939
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1203MC-CAB-AX
Manufacturer Part Number
UPD78F1203MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1203MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
RENESAS
Quantity:
15 000
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
NEC
Quantity:
20 000
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21.4.2 When used as interrupt
(1) When detecting level of supply voltage (V
• When starting operation
• When stopping operation
Figure 21-7 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <8> above.
Be sure to clear (0) LVION by using a 1-bit memory manipulation instruction.
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
Mask the LVI interrupt (LVIMK = 1).
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level
Confirm that “supply voltage (V
(V
selection register (LVIS).
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
Use software to wait for the following periods of time (Total 210
or “supply voltage (V
(LVIF) of LVIM.
Clear the interrupt request flag of LVI (LVIIF) to 0.
Release the interrupt mask flag of LVI (LVIMK).
Execute the EI instruction (when vector interrupts are used).
• Operation stabilization time (10
• Minimum pulse width (200
DD
)) (default value).
CHAPTER 21 LOW-VOLTAGE DETECTOR
DD
) < detection voltage (V
User’s Manual U19678EJ1V1UD
μ
s (MIN.))
DD
DD
) ≥ detection voltage (V
)
μ
s (MAX.))
LVI
)” when detecting the rising edge of V
LVI
)” when detecting the falling edge of V
μ
s).
DD
, at bit 0
937
DD
,
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