MAXQ7670ATL/V+ Maxim Integrated Products, MAXQ7670ATL/V+ Datasheet - Page 19

• Manufacturer Part Number: MAXQ7670ATL/V+
• Description: IC MCU W/10BIT ADC 40TQFN-EP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7670ATL/V+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-TQFN Exposed Pad
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, JTAG, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The MAXQ7670 ADC uses a fully differential SAR con-
version technique and an integrated T/H (track and
hold) block to convert voltage signals into a 10-bit digi-
tal result. Both single-ended and differential configura-
tions are implemented using an analog input channel
multiplexer that supports 8 single-ended or 4 differen-
tial channels.
In single-ended mode, the mux selects from either of
the ground-referenced analog inputs AIN0–AIN7. In dif-
ferential input configuration, analog inputs are selected
from the following pairs: AIN0/AIN1, AIN2/AIN3,
AIN4/AIN5, and AIN6/AIN7. Table 1 shows the single-
ended and differential input configurations possible for
the ADC mux.
A SAR conversion in the MAXQ7670 has different T/H
cycles depending on whether a gain of 1 (bypass) or a
gain of 16 (PGA enabled) is selected.
Table 1. ADC Mux Input Configurations
SAR CHANNEL
ACNT[14:11])
(REGISTER
SELECT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
______________________________________________________________________________________
SIGNAL CHANNEL
Analog Input Track and Hold
INTO ADC
PGA, 64KB Flash, and CAN Interface
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN0
AIN2
AIN4
AIN6
—
—
—
—
Microcontroller with 10-Bit ADC,
CHANNEL INTO
REFERENCE
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
ADC
AIN1
AIN3
AIN5
AIN7
—
—
—
—
In gain = 1V/V, the conversion has a two-stage T/H
cycle. In track mode, a positive input capacitor con-
nects to the signal channel. A negative input capacitor
connects to the reference channel. After the T/H enters
hold mode, the difference between the signal and the
reference channel is converted to a 10-bit value. This
two-stage cycle takes 16 SARCLKs to complete.
In gain = 16V/V, the conversion has a three-stage T/H
cycle: amplification, ADC track, and ADC hold. First,
the PGA tracks the selected input and reference sig-
nals. The PGA amplifies the difference between the two
signals and holds the result for the next stage, ADC
track. The ADC tracks and converts the PGA result into
a 10-bit value. The SAR operation itself does not
change irrespective of the chosen gain. This three-
stage cycle takes 26.5 SARCLKs to complete. Figure 5
shows the conversion timing differences between gain
= 1V/V and gain = 16V/V.
Single-ended measurement on AIN0
Single-ended measurement on AIN1
Single-ended measurement on AIN2
Single-ended measurement on AIN3
Single-ended measurement on AIN4
Single-ended measurement on AIN5
Single-ended measurement on AIN6
Single-ended measurement on AIN7
Reserved
Reserved
AIN0/AIN1
AIN2/AIN3
AIN4/AIN5
AIN6/AIN7
Reserved
VCIM differential zero offset trim
MEASUREMENT TYPE
Gain = 16V/V
Gain = 1V/V
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