MAXQ7670ATL/V+ Maxim Integrated Products, MAXQ7670ATL/V+ Datasheet - Page 31

• Manufacturer Part Number: MAXQ7670ATL/V+
• Description: IC MCU W/10BIT ADC 40TQFN-EP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7670ATL/V+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-TQFN Exposed Pad
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, JTAG, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 3. System Register Bit and Reset Values
*Bits indicated by an "s" are only affected by a POR and not by other forms of reset. These bits are set to 0 after a POR. Refer to the
MAXQ7670 User’s Guide for more information.
PFX[n] (0..15)
REGISTER
A[n] (0..15)
WDCN
CKCN
GRXL
LC[0]
LC[1]
OFFS
DP[0]
DP[1]
APC
DPC
GRL
GRS
GRH
PSF
IMR
GR
AP
SC
BP
IIR
SP
FP
IC
IP
IV
GR.15
GR.7
GR.7
15
—
—
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
______________________________________________________________________________________
GR.14
GR.6
GR.7
14
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.13
PGA, 64KB Flash, and CAN Interface
GR.5
GR.7
13
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.12
GR.4
GR.7
12
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Microcontroller with 10-Bit ADC,
GR.11
GR.3
GR.7
11
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.10
GR.2
GR.7
10
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.9
GR.1
GR.7
—
—
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.8
GR.0
GR.7
—
—
REGISTER BIT
8
0
PFX[n] (16 Bits)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DP[0] (16 Bits)
DP[1] (16 Bits)
LC[0] (16 Bits)
LC[1] (16 Bits)
A[n] (16 Bits)
BP (16 Bits)
FP (16 Bits)
IP (16 Bits)
IV (16 Bits)
GR.15
GR.15
GR.7
GR.7
GR.7
POR
CLR
TAP
IMS
IIS
XT
—
—
s*
s*
—
—
Z
7
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.14
GR.14
EWDI
GR.6
GR.6
GR.6
IDS
—
—
—
—
—
—
s*
—
—
6
0
0
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RGMD
CGDS
GR.13
GR.13
CDA1
WD1
GR.5
GR.5
GR.5
IM5
—
—
—
II5
—
—
s*
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WBS2
GR.12
GR.12
CDA0
STOP
GPF1
WD0
GR.4
GR.4
GR.4
IM4
—
—
—
II4
—
OFFS (8 Bits)
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
WBS1
GR.11
GR.11
GPF0
WDIF
GR.3
GR.3
GR.3
SWB
UPA
IM3
II3
—
—
3
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
MOD2
PMME
WTRF
WBS0
GR.10
GR.10
GR.2
GR.2
GR.2
ROD
IM2
OV
—
II2
s*
2
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
AP (4 Bits)
SP (4 Bits)
SDPS1
MOD1
GR.1
GR.1
GR.9
GR.9
GR.1
PWL
EWT
CD1
INS
IM1
II1
s*
s*
C
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDPS0
MOD0
GR.0
GR.0
GR.8
GR.8
GR.0
RWT
CD0
IGE
IM0
—
II0
0
0
0
E
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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