UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 504

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
16.4 Registers
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The following registers are used to control CSIBn.
• CSIBn control register 0 (CBnCTL0)
• CSIBn control register 1 (CBnCTL1)
• CSIBn control register 2 (CBnCTL2)
• CSIBn status register (CBnSTR)
(1) CSIBn control register 0 (CBnCTL0)
CBnCTL0 is a register that controls the CSIBn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
(n = 0 to 4)
CBnCTL0
After reset: 01H
Note These bits can only be rewritten when the CBnPWR bit = 0.
Caution To forcibly suspend transmission/reception, clear the CBnPWR bit
CBnPWR
CBnRXE
CBnPWR
CBnTXE
• The CBnPWR bit controls the CSIBn operation and resets the internal circuit.
• The SOBn output is low level when the CBnTXE bit is 0.
• When the CBnRXE bit is cleared to 0, no reception complete interrupt is output
even when the prescribed data is transferred in order to disable the receive
operation, and the receive data (CBnRX register) is not updated.
< >
0
1
0
1
0
1
However, CBnPWR bit = 1 can also be set at the same time as rewriting
these bits.
Note
Note
to 0 instead of the CBnRXE and CBnTXE bits.
At this time, the clock output is stopped.
R/W
CBnTXE
Disable CSIBn operation and reset the CBnSTR register
Enable CSIBn operation
Disable transmit operation
Enable transmit operation
Disable receive operation
Enable receive operation
< >
Note
Address: CB0CTL0 FFFFFD00H, CB1CTL0 FFFFFD10H,
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
CBnRXE
Specification of transmit operation disable/enable
Specification of receive operation disable/enable
Specification of CSIBn operation disable/enable
< >
CB2CTL0 FFFFFD20H, CB3CTL0 FFFFFD30H,
CB4CTL0 FFFFFD40H
Note
CBnDIR
< >
Note
0
0
CBnTMS
Note
CBnSCE
< >
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