SAK-C167CR-L33M HA+ Infineon Technologies, SAK-C167CR-L33M HA+ Datasheet - Page 70

• Manufacturer Part Number: SAK-C167CR-L33M HA+
• Description: IC MCU 16BIT 2KB XRAM MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C167CR-L33M HA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144- BSQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 9
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 33.0 MHz
• Sram (incl. Cache): 4.0 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 16
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: K167CRL33MHAZNP; K167CRL33MHAZXP; SAKC167CRL33MHA; SP000017997; SP000103460; SP000103461

The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and
For a period of N × TCL the minimum value is computed using the corresponding
deviation D
(N × TCL)
where N = number of consecutive TCLs and 1 ≤ N ≤ 40.
So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D
and (3TCL)
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see
Figure 11
Data Sheet
±26.5
±30
±20
±10
ns
±1
min
Max. jitter
1
N
min
This approximated formula is valid for
1 N
:
= N × TCL
Approximated Maximum Accumulated PLL Jitter
= 3TCL
5
40 and 10 MHz
D
N
NOM
10
NOM
- 1.288 ns = 58.7 ns (@
- D
f
CPU
N
, D
33 MHz.
N
[ns] = ±(13.3 + N × 6.3) /
Figure
20
68
11).
f
CPU
3
= (13.3 + 3 × 6.3) / 25 = 1.288 ns,
= 25 MHz).
f
CPU
Electrical Parameters
40
[MHz],
10 MHz
16 MHz
20 MHz
25 MHz
33 MHz
V3.3, 2005-02
Figure
C167CR
MCD04413
C167SR
N
11).
(1)