SAK-C167CR-L33M HA+ Infineon Technologies, SAK-C167CR-L33M HA+ Datasheet - Page 75
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SAK-C167CR-L33M HA+
Manufacturer Part Number
SAK-C167CR-L33M HA+
Description
IC MCU 16BIT 2KB XRAM MQFP-144
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAB-C167CR-LM_HA.pdf
(89 pages)
Specifications of SAK-C167CR-L33M HA+
Core Processor
C166
Core Size
16-Bit
Speed
33MHz
Connectivity
CAN, EBI/EMI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
144- BSQFP
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN, SSC, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
111
Number Of Timers
9
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Packages
PG-MQFP-144
Max Clock Frequency
33.0 MHz
Sram (incl. Cache)
4.0 KByte
Can Nodes
1
A / D Input Lines (incl. Fadc)
16
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
K167CRL33MHAZNP
K167CRL33MHAZXP
SAKC167CRL33MHA
SP000017997
SP000103460
SP000103461
K167CRL33MHAZXP
SAKC167CRL33MHA
SP000017997
SP000103460
SP000103461
Table 19
Parameter
Output delay from CLKOUT falling edge
Valid for: address, BHE, early CS, write data out, ALE
Output delay from CLKOUT rising edge
Valid for: latched CS, ALE low
Output delay from CLKOUT rising edge
Valid for: WR low (no RW delay), RD low (no RW
delay)
Output delay from CLKOUT falling edge
Valid for: RD/WR low (with RW delay), RD high (with
RW delay)
Input setup time to CLKOUT falling edge
Valid for: read data in
Input hold time after CLKOUT falling edge
Valid for: read data in
Output hold time after CLKOUT falling edge
Valid for: address, BHE, early CS
Output hold time after CLKOUT edge
Valid for: write data out
Output delay from CLKOUT falling edge
Valid for: WR high
Turn off delay after CLKOUT edge
Valid for: write data out
Turn on delay after CLKOUT falling edge
Valid for: write data out
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
2) Due to comparable propagation delays (at comparable capacitive loads) the address does not change before
3) Not subject to production test - verified by design/characterization.
Data Sheet
of RD. Therefore the read data may be removed immediately after the rising edge of RD. Address changes
before the end of RD have also no impact on (demultiplexed) read cycles.
WR goes high. The minimum output delay (
External Bus Cycle Timing (Operating Conditions apply)
1)
2)
3)
tc
3)
17min
3)
) is therefore the actual value of
73
Symbol
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
10
11
12
13
14
15
17
18
19
20
21
CC -2
CC -2
CC -2
CC -2
SR 14
SR 0
CC -2
CC -2
CC -2
CC –
CC -5
Electrical Parameters
Min.
tc
19
.
Limits
Max.
11
6
8
6
–
–
6
–
4
7
–
V3.3, 2005-02
C167CR
C167SR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns