PIC16C74-04/P Microchip Technology, PIC16C74-04/P Datasheet - Page 82

• Manufacturer Part Number: PIC16C74-04/P
• Description: MICRO CTRL 4K 4MHZ OTP 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C74-04/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

PIC16C7X
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode (SSPCON<3:0> = 04h)
and the TRISA<5> bit must be set the for synchro-
nous slave mode to be enabled. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
output. If the SS pin is taken low without resetting
SPI mode, the transmission will continue from the
FIGURE 11-5: SPI MODE TIMING, MASTER MODE OR SLAVE MODE W/O SS CONTROL
FIGURE 11-6: SPI MODE TIMING, SLAVE MODE WITH SS CONTROL
TABLE 11-1:
DS30390E-page 82
Address
0Bh,8Bh
0Ch
8Ch
87h
13h
14h
85h
94h
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
SCK
(CKP = 0)
SCK
(CKP = 1)
2: The PIC16C72 does not have a Parallel Slave Port or USART, these bits are unimplemented, read as '0'.
SCK
(CKP = 0)
SCK
(CKP = 1)
SS
SSPIF
SDO
SSPIF
SDI
SDO
Name
INTCON
PIR1
PIE1
TRISC
SSPBUF
SSPCON
TRISA
SSPSTAT
SDI
REGISTERS ASSOCIATED WITH SPI OPERATION
PSPIE
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
PSPIF
WCOL
Bit 7
GIE
—
—
bit7
bit7
(1,2)
(1,2)
bit7
bit7
SSPOV SSPEN
PEIE
ADIF
ADIE
Bit 6
—
—
bit6
bit6
PORTA Data Direction Register
RCIE
RCIF
Bit 5
T0IE
D/A
72 73 73A 74 74A 76 77
Applicable Devices
(2)
(2)
bit5
TXIF
TXIE
bit5
INTE
Bit 4
CKP
P
(2)
(2)
bit4
SSPM3 SSPM2 SSPM1
SSPIF
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
RBIE
Bit 3
bit4
S
point at which it was taken high. External pull-up/
pull-down resistors may be desirable, depending on the
application.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
bit3
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
Bit 2
T0IF
R/W
bit3
bit2
INTF
Bit 1
UA
bit2
SSPM0 0000 0000 0000 0000
RBIF
Bit 0
bit1
BF
1997 Microchip Technology Inc.
bit1
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
--00 0000 --00 0000
Value on:
POR,
BOR
bit0
bit0
bit0
bit0
Value on
all other
resets