PIC16C554/JW Microchip Technology, PIC16C554/JW Datasheet - Page 43

• Manufacturer Part Number: PIC16C554/JW
• Description: IC MCU EPROM 512X14 18CDIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C554/JW

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 896B (512 x 14)
• Program Memory Type: EPROM, UV
• Ram Size: 80 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-CDIP (0.300", 7.62mm) Window
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

6.5
The PIC16C55X has 3 sources of interrupt:
• External interrupt RB0/INT
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB7:RB4)
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on RESET.
The “Return from Interrupt” instruction,
the interrupt routine as well as sets the GIE bit, which
re-enables RB0/INT interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
FIGURE 6-11:
 2002 Microchip Technology Inc.
Interrupts
INTERRUPT LOGIC
RBIE
INTE
RBIF
INTF
T0IE
T0IF
GIE
RETFIE
, exits
Preliminary
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 6-12).
The latency is the same for one or two cycle
instructions. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests. Individual interrupt
flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
Note 1: Individual interrupt flag bits are set
2: When an instruction that clears the GIE
regardless
corresponding mask bit or the GIE bit.
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a NOP
in the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit
is set again.
(If in SLEEP mode)
Wake-up
Interrupt
to CPU
PIC16C55X
of
the
status
DS40143D-page 41
of
their