AT91M43300-25CI Atmel, AT91M43300-25CI Datasheet - Page 15

• Manufacturer Part Number: AT91M43300-25CI
• Description: IC ARM7 MCU 144 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M43300-25CI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

18. AT91M43300 Errata
18.1
1322B–ATARM–12-Dec-05
Warning: Additional NWAIT Constraints
Internal Product
Reference 55560A
These errata are applicable to:
When the NWAIT signal is asserted during an external memory access, the following EBI behav-
ior is correct:
In these cases, the access is delayed as required by NWAIT and the access operations are cor-
rectly performed.
In other cases, the following erroneous behavior occurs:
At maximum speed, asserting the NWAIT in the first access cycle is not possible, as the sum of
the timings “MCKI Falling to Chip Select” and “NWAIT setup to MCKI rising” are generally higher
than one half of a clock period. This leads to using at least one standard wait state. However,
this is not sufficient except to perform byte or half-word read accesses. Word and write accesses
require at least two standard wait states.
The following waveforms further explain the issue:
• 144-ball BGA devices with the following markings:
• NWAIT is asserted before the first rising edge of the master clock and respects the NWAIT to
• NWAIT is sampled inactive and at least one standard wait state remains to be executed, even
• 32-bit read accesses are not managed correctly and the first 16-bit data sampling takes into
• During write accesses of any type, the NWE rises on the rising edge of the last cycle as
AT91M43300 Lit° 1322
AT91M43300,Electrical Characteristics, Rev. 1090B–05/00
MCKI rising setup timing as defined in the Electrical Characteristics datasheet.
if NWAIT does not meet the NWAIT to first MCKI rising setup timing (i.e., NWAIT is asserted
only on the second rising edge of MCKI).
account only the standard wait states. 16- and 8-bit accesses are not affected.
defined by the programmed number of wait states. However, NWAIT assertion does affect the
length of the total access. Only the NWE pulse length is inaccurate.
AT91M43300-25CI
AT91M43300-25CJ
AT91M43300
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