AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 111

• Manufacturer Part Number: AT91M63200-25AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M63200-25AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-TQFP, 176-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

TC: Timer/Counter
The AT91M63200 features two Timer/Counter blocks, each
containing three identical 16-bit Timer/Counter channels.
Each channel can be independently programmed to per-
form a wide range of functions including frequency mea-
surement, event counting, interval measurement, pulse
generation, delay timing and pulse width modulation.
Each Timer/Counter channel has three external clock
inputs, five internal clock inputs, and two multi-purpose
input/output signals which can be configured by the user.
Each channel drives an internal interrupt signal which can
be programmed to generate processor interrupts via the
AIC (Advanced Interrupt Controller).
Figure 53. TC Block Diagram
MCKI/2
MCKI/8
MCKI/32
MCKI/128
MCKI/1024
Timer/Counter Block
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TIOA1
TIOA2
TIOA0
TIOA2
TIOA0
TIOA1
TC0XC0S
TC1XC1S
TC2XC2S
XC0
XC1
XC2
XC0
XC1
XC2
XC0
XC1
XC2
Timer/Counter
Timer/Counter
Timer/Counter
Channel 0
Channel 1
Channel 2
The Timer/Counter block has two global registers which act
upon all three TC channels. The Block Control Register
allows the three channels to be started simultaneously with
the same instruction. The Block Mode Register defines the
external clock inputs for each Timer/Counter channel,
allowing them to be chained.
Each Timer/Counter block operates independently and has
a complete set of block and channel registers. Since they
are identical in operation, only one block is described below
(see "Timer/Counter Description" on page 113). The inter-
nal configuration of a single Timer/Counter block is shown
in Figure 53.
SYNC
SYNC
SYNC
TIOA
TIOB
TIOA
TIOB
TIOA
TIOB
INT
INT
INT
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Advanced
Controller
Interrupt
AT91M63200
Parallel I/O
Controller
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
111