AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 17

• Manufacturer Part Number: AT91M63200-25AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M63200-25AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-TQFP, 176-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Data Float Wait State
Some memory devices are slow to release the external
bus. For such devices it is necessary to add wait states
(data float waits) after a read access before starting a write
access or a read access to a different external memory.
The data float output time (t
device is programmed in the TDF field of the EBI_CSR reg-
ister for the corresponding chip select. The value (0-7 clock
cycles) indicates the number of data float waits to be
inserted and represents the time allowed for the data out-
put to go high impedance after the memory is disabled.
Data float wait states do not delay internal memory
accesses. Hence, a single access to an external memory
with long t
from internal memory.
The EBI keeps track of the programmed external data float
time during internal accesses to ensure that the external
memory system is not accessed while it is still busy.
Figure 18. Data Float Output Time
Notes:
Internal memory accesses and consecutive accesses to
the same external memory do not have added data float
wait states.
D0-D15
ADDR
MCKI
NCS
NRD
1. Early read protocol
2. Standard read protocol
DF
will not slow down the execution of a program
(1)
DF
) for each external memory
(2)
t
DF
NWAIT
External Wait
The NWAIT input can be used to add wait states at any
time. NWAIT is active low and is detected on the rising
edge of the clock.
If NWAIT is low at the rising edge of the clock, the EBI adds
a wait state and changes neither the output signals nor its
internal counters and state. When NWAIT is de-asserted,
the EBI finishes the access sequence.
Figure 19. External Wait
Notes:
The NWAIT signal must meet setup and hold requirements
on the rising edge of the clock.
ADDR
MCKI
NWE
NRD
NCS
1. Early read protocol
2. Standard read protocol
(1)
(2)
AT91M63200
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