AT90LS8535-4PI Atmel, AT90LS8535-4PI Datasheet - Page 68
![IC MCU 8K 4MHZ A/D LV IT 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
AT90LS8535-4PI
Manufacturer Part Number
AT90LS8535-4PI
Description
IC MCU 8K 4MHZ A/D LV IT 40DIP
Manufacturer
Atmel
Series
AVR® 90LSr
Specifications of AT90LS8535-4PI
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Analog-to-Digital
Converter
Feature list
68
AT90S/LS8535
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The AT90S8535 features a 10-bit successive approximation ADC. The ADC is con-
nected to an 8-channel Analog Multiplexer that allows each pin of Port A to be used as
an input for the ADC. The ADC contains a Sample and Hold Amplifier that ensures that
the input voltage to the ADC is held at a constant level during conversion. A block dia-
gram of the ADC is shown in Figure 45.
The ADC has two separate analog supply voltage pins, AVCC and AGND. AGND must
be connected to GND and the voltage on AV
V
An external reference voltage must be applied to the AREF pin. This voltage must be in
the range 2V - AV
Figure 45. Analog-to-Digital Converter Block Schematic
ADC7
ADC5
ADC3
ADC6
ADC4
ADC2
ADC1
ADC0
CC
10-bit Resolution
0.5 LSB Integral Non-linearity
±2 LSB Absolute Accuracy
65 - 260 µs Conversion Time
Up to 15 kSPS at Maximum Resolution
8 Multiplexed Input Channels
Rail-to-Rail Input Range
Free Running or Single Conversion Mode
Interrupt on ADC Conversion Complete
Sleep Mode Noise Canceler
AREF
. See “ADC Noise Canceling Techniques” on page 74 on how to connect these pins.
8-BIT DATA BUS
CHANNEL
MUX
8-
CC
.
+
10-BIT DAC
-
SAMPLE & HOLD
COMPARATOR
ADC MULTIPLEXER
SELECT (ADMUX)
CC
ADC CTRL & STATUS
ADC CONVERSION
REGISTER (ADCSR)
must not differ more than ±0.3V from
COMPLETE IRQ
PRESCALER
CONVERSION LOGIC
15
ADC DATA REGISTER
(ADCH/ADCL)
1041H–11/01
0
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