AT90S8515A-4JC Atmel, AT90S8515A-4JC Datasheet - Page 86
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AT90S8515A-4JC
Manufacturer Part Number
AT90S8515A-4JC
Description
IC MCU 8K FLSH 4MHZ LV 44PLCC
Manufacturer
Atmel
Series
AVR® 90Sr
Datasheets
1.AT90S8515-4AC.pdf
(112 pages)
2.AT90S8515-4AC.pdf
(4 pages)
3.AT90S8515-4AC.pdf
(4 pages)
Specifications of AT90S8515A-4JC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Serial Downloading
Serial Programming
Algorithm
86
AT90S8515
Both the program and data memory arrays can be programmed using the SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and
MISO (output). See Figure 64. After RESET is set low, the Programming Enable instruc-
tion needs to be executed first before program/erase instructions can be executed.
Figure 64. Serial Programming and Verify
For the EEPROM, an auto-erase cycle is provided within the self-timed Write instruction
and there is no need to first execute the Chip Erase instruction. The Chip Erase instruc-
tion turns the content of every memory location in both the program and EEPROM
arrays into $FF.
The program and EEPROM memory arrays have separate address spaces: $0000 to
$0FFF (AT90S8515) for program memory and $0000 to $01FF (AT90S8515) for
EEPROM memory.
Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected
across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock
(SCK) input are defined as follows:
Low: > 2 XTAL1 clock cycles
High: > 2 XTAL1 clock cycles
When writing serial data to the AT90S8515, data is clocked on the rising edge of SCK.
When reading data from the AT90S8515, data is clocked on the falling edge of SCK.
See Figure 65, Figure 66 and Table 33 on page 89 for timing details.
To program and verify the AT90S8515 in the Serial Programming Mode, the following
sequence is recommended (see 4-byte instruction formats in Table 32 ):
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Program-
3. The serial programming instructions will not work if the communication is out of
Apply power between V
tal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the
XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held
low during power-up. In this case, RESET must be given a positive pulse of at least
two XTAL1 cycles duration after SCK has been set to “0”.
ming Enable serial instruction to the MOSI (PB5) pin.
synchronization. When in sync, the second byte ($53) will echo back when issu-
CLOCK INPUT
GND
CC
and GND while RESET and SCK are set to “0”. If a crys-
GND
RESET
XTAL1
AT90S8515
VCC
PB7
PB6
PB5
2.7 - 6.0V
SCK
MISO
MOSI
0841G–09/01