PIC16C72-10E/SP Microchip Technology, PIC16C72-10E/SP Datasheet - Page 33
![IC MCU OTP 2KX14 A/D PWM 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16C72-10E/SP
Manufacturer Part Number
PIC16C72-10E/SP
Description
IC MCU OTP 2KX14 A/D PWM 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C72-04SO.pdf
(289 pages)
4.PIC16C72-04SO.pdf
(125 pages)
5.PIC16C72-04SO.pdf
(8 pages)
Specifications of PIC16C72-10E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16C72-04SO PDF datasheet #3
- PIC16C72-04SO PDF datasheet #4
- PIC16C72-04SO PDF datasheet #5
- Current page: 33 of 289
- Download datasheet (3Mb)
4.2.2.4
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 4-10: PIE1 REGISTER PIC16C72 (ADDRESS 8Ch)
1997 Microchip Technology Inc.
bit7
bit 7:
bit 6:
bit 5-4: Unimplemented: Read as '0'
bit 3:
bit 2:
bit 1:
bit 0:
U-0
—
PIE1 REGISTER
Applicable Devices
72 73 73A 74 74A 76 77
Unimplemented: Read as '0'
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R/W-0
ADIE
U-0
—
U-0
—
SSPIE
R/W-0
CCP1IE
R/W-0
TMR2IE
R/W-0
Note:
TMR1IE
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
read as ‘0’
PIC16C7X
DS30390E-page 33
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