PIC16C745/JW Microchip Technology, PIC16C745/JW Datasheet - Page 110
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PIC16C745/JW
Manufacturer Part Number
PIC16C745/JW
Description
IC MCU EPROM8KX14 USB A/D 28CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C745-ISP.pdf
(165 pages)
3.PIC16C745-ISP.pdf
(6 pages)
4.PIC16C745-ISP.pdf
(6 pages)
Specifications of PIC16C745/JW
Core Processor
PIC
Core Size
8-Bit
Speed
24MHz
Connectivity
SCI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
EPROM, UV
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.35 V ~ 5.25 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C745/JW
Manufacturer:
MICROCHIP
Quantity:
51
Part Number:
PIC16C745/JW
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16C745/765
13.8
The Watchdog Timer is a free running on-chip dedi-
cated oscillator, which does not require any external
components. The WDT will run, even if the clock on the
OSC1/CLKIN and OSC2/CLKOUT pins of the device
has been stopped, for example, by execution of a
SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and resume normal operation (Watchdog
Timer Wake-up).
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 13.1).
13.8.1
The WDT has a nominal time-out period of 18 ms
(parameter #31, T
temperature, V
time-out periods are desired, a prescaler with a division
FIGURE 13-7: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 13-8:
DS41124C-page 110
Address
2007h
81h,181h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1:
Note: PSA and PS<2:0> are bits in the OPTION register.
Watchdog Timer (WDT)
WDT PERIOD
See Register 13-1 for operation of these bits.
Name
Config. bits
OPTION_REG
DD
WDT
SUMMARY OF WATCHDOG TIMER REGISTERS
and process variations. If longer
). The time-out periods vary with
WDT Timer
Enable Bit
WDT
RBPU
Bit 7
—
From TMR0 Clock Source
(Figure 6-1)
BODEN
INTEDG
Bit 6
(1)
0
1
T0CS
Bit 5
CP1
PSA
M
U
X
Preliminary
T0SE
Bit 4
CP0
PWRTE
ratio of up to 1:128 can be assigned to the WDT under
software control by writing to the OPTION register.
Time-out periods up to 128 T
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT. In addition,
the SLEEP instruction prevents the WDT from generat-
ing a RESET, but will allow the WDT to wake the device
from SLEEP mode.
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
13.8.2
It should also be taken into account that under worst
case conditions (V
max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
0
Bit 3
Note:
PSA
Time-out
8 - to - 1 MUX
MUX
WDT
Postscaler
(1)
WDT PROGRAMMING CONSIDERATIONS
WDTE
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
1
Bit 2
PS2
8
DD
Bit 1
PS1
PLL
PSA
To TMR0 MUX
(Figure 6-1)
= Min., Temperature = Max., and
2000 Microchip Technology Inc.
FOSC0
PS<2:0>
Bit 0
PS0
WDT
can be realized.
1111 1111 1111 1111
POR, BOR
Value on
Value on
All Other
Resets