AT89C1051-24SC Atmel, AT89C1051-24SC Datasheet - Page 6

• Manufacturer Part Number: AT89C1051-24SC
• Description: IC MCU 1KB FLASH 24MHZ 20-SOIC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C1051-24SC

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Peripherals: LED
• Number Of I /o: 15
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: AT89C105124SC

Programming Algorithm: To program the AT89C1051,
the following sequence is recommended.
1. Power-up sequence:
2. Set pin RST to ‘H’
3. Apply the appropriate combination of ‘H’ or ‘L’ logic
To Program and Verify the Array:
4. Apply data for Code byte at location 000H to P1.0 to
5. Raise RST to 12V to enable programming.
6. Pulse P3.2 once to program a byte in the PEROM array
7. To verify the programmed data, lower RST from 12V to
8. To program a byte at the next address location, pulse
9. Repeat steps 5 through 8, changing data and advancing
10.Power-off sequence:
Flash Programming Modes
Note:
4-8
Write Code Data
Read Code Data
Write Lock
Chip Erase
Read Signature Byte
Apply power between V
Set RST and XTAL1 to GND
Set pin P3.2 to ‘H’
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the
programming operations shown in the PEROM Pro-
gramming Modes table.
P1.7.
or the lock bits. The byte-write cycle is self-timed and
typically takes 1.2 ms.
logic ‘H’ level and set pins P3.3 to P3.7 to the appropiate
levels. Output data can be read at the port P1 pins.
XTAL1 pin once to advance the internal address counter.
Apply new data to the port P1 pins.
the address counter for the entire 1K byte array or until
the end of the object file is reached.
set XTAL1 to ‘L’
set RST to ‘L’
Turn V
1. The internal PEROM address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at
2. Chip Erase requires a 10-ms PROG pulse.
3. P3.1 is pulled Low during programming to indicate RDY/BSY.
CC
XTAL1 pin.
power off
Mode
(1)(3)
(1)
AT89C1051
CC
Bit-1
Bit-2
and GND pins
RST/VPP
12V
12V
12V
12V
H
H
P3.2/PROG
H
H
Data Polling: The AT89C1051 features Data Polling to
indicate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written data on P1.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Ready/Busy: The Progress of byte programming can also
be monitored by the RDY/BSY output signal. Pin P3.1 is
pulled low after P3.2 goes High during programming to indi-
cate BUSY. P3.1 is pulled High again when programming is
done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been
programmed code data can be read back via the data lines
for verification:
1. Reset the internal address counter to 000H by bringing
2. Apply the appropriate control signals for Read Code data
3. Pulse pin XTAL1 once to advance the internal address
4. Read the next code data byte at the port P1 pins.
5. Repeat steps 3 and 4 until the entire array is read.
The lock bits cannot be verified directly. Verification of the
lock bits is achieved by observing that their features are
enabled.
RST from ’L’ to ’H’.
and read the output data at the port P1 pins.
counter.
(2)
P3.3
H
H
H
L
L
L
P3.4
H
H
H
L
L
L
P3.5
H
H
H
L
L
L
P3.7
H
H
H
L
L
L