AT89LS53-12PI Atmel, AT89LS53-12PI Datasheet - Page 8
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AT89LS53-12PI
Manufacturer Part Number
AT89LS53-12PI
Description
IC 8051 MCU FLASH 12K 40DIP
Manufacturer
Atmel
Series
89LSr
Datasheet
1.AT89LS53-12AC.pdf
(35 pages)
Specifications of AT89LS53-12PI
Core Processor
8051
Core Size
8-Bit
Speed
12MHz
Connectivity
SPI, UART/USART
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
AT89LS5312PI
Table 4. SPCR—SPI Control Register
Table 5. SPSR—SPI Status Register
8
SPCR Address = D5H
Symbol
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR0
SPR1
SPSR Address = AAH
Symbol
SPIF
WCOL
Bit
Bit
SPIE
7
SPIF
7
AT89LS53
Function
SPI Interrupt Enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE
= 1 and ES = 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts.
SPI Enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5,
P1.6, and P1.7. SPI = 0 disables the SPI channel.
Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.
Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects Slave SPI mode.
Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low
when not transmitting. Please refer to figure on SPI Clock Phase and Polarity Control.
Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between
master and slave. Please refer to figure on SPI Clock Phase and Polarity Control.
SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1 and
SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency, F
follows:
Function
SPI Interrupt Flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if
SPIE = 1 and ES = 1. The SPIF bit is cleared by reading the SPI status register with SPIF and WCOL bits
set, and then accessing the SPI data register.
Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During
data transfer, the result of reading the SPDR register may be incorrect, and writing to it has no effect. The
WCOL bit (and the SPIF bit) are cleared by reading the SPI status register with SPIF and WCOL set, and
then accessing the SPI data register.
SPR1
0
0
1
1
SPE
6
WCOL
6
SPR0
0
1
0
1
5
—
5
DORD
SCK = F
MSTR
4
—
4
OSC.
128
16
64
4
divided by
CPOL
3
—
3
CPHA
2
—
2
SPR1
1
—
1
Reset Value = 00XX XXXXB
Reset Value = 0000 01XXB
SPR0
0
—
0
0851C–MICRO–3/06
OSC.
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