AT91M55800-33CI Atmel, AT91M55800-33CI Datasheet - Page 14

• Manufacturer Part Number: AT91M55800-33CI
• Description: IC ARM7 MCU 176 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800-33CI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT91M5580033CI

IEEE 1149.1 JTAG Boundary-
scan
Memory Controller
Internal Memories
Boot Mode Select
Remap Command
14
AT91M55800A
JTAG Boundary-scan is enabled when JTAGSEL is high. The functions SAMPLE,
EXTEST and BYPASS are implemented. There is no JTAG chip ID. The Special Func-
tion module provides a chip ID which is independent of JTAG.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must
be performed (NRST and NTRST) after JTAGSEL is changed.
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes
the internal 32-bit address bus and defines three address spaces:
•
•
•
In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.
The AT91M55800A microcontroller integrates an 8-Kbyte primary SRAM bank. This
memory bank is mapped at address 0x0 (after the remap command), allowing
ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software.
The rest of the bank can be used for stack allocation (to speed up context saving and
restoring), or as data and program storage for critical algorithms. All internal memory is
32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or word
(32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or
ARM instructions is supported and internal memory can store twice as many Thumb
instructions as ARM ones.
The ARM reset vector is at address 0x0. After the NRST line is released, the
ARM7TDMI executes the instruction stored at this address. This means that this
address must be mapped in nonvolatile memory after the reset.
The input level on the BMS pin during the last 10 clock cycles before the rising edge of
the NRST selects the type of boot memory (see Table 5).
The BMS pin is multiplexed with the I/O line PB18 that can be programmed after reset
like any standard PIO line.
Table 6. Boot Mode Select
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction,
Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to
allow these vectors to be redefined dynamically by the software, the AT91M55800A
microcontroller uses a remap command that enables switching between the boot mem-
ory and the internal RAM bank addresses. The remap command is accessible through
the EBI User Interface, by writing one in RCB of EBI_RCR (Remap Control Register).
Performing a remap command is mandatory if access to the other external devices (con-
nected to chip selects 1 to 7) is required. The remap operation can only be changed
back by an internal reset or an NRST assertion.
BMS
1
0
Internal memories in the four lowest megabytes
Middle space reserved for the external devices (memory or peripherals) controlled
by the EBI
Internal peripherals in the four highest megabytes
Boot Mode
External 8-bit memory on NCS0
External 16-bit memory on NCS0
1745CS–ATARM–05/02