AT91M55800-33CI Atmel, AT91M55800-33CI Datasheet - Page 16

• Manufacturer Part Number: AT91M55800-33CI
• Description: IC ARM7 MCU 176 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800-33CI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT91M5580033CI

Peripherals
Peripheral Registers
Peripheral Interrupt Control
Peripheral Data Controller
16
AT91M55800A
The AT91M55800A peripherals are connected to the 32-bit wide Advanced Peripheral
Bus. Peripheral registers are only word accessible. Byte and half-word accesses are not
supported. If a byte or a half-word access is attempted, the memory controller automati-
cally masks the lowest address bits and generates a word access.
Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte
address space).
The following registers are common to all peripherals:
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•
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Unused bits in the peripheral registers are shown as “–” and must be written at 0 for
upward compatibility. These bits read 0.
The Interrupt Control of each peripheral is controlled from the status register using the
interrupt mask. The status register bits are ANDed to their corresponding interrupt mask
bits and the result is then ORed to generate the Interrupt Source signal to the Advanced
Interrupt Controller.
The interrupt mask is read in the Interrupt Mask Register and is modified with the Inter-
rupt Enable Register and the Interrupt Disable Register. The enable/disable/status (or
mask) makes it possible to enable or disable peripheral interrupt sources with a non-
interruptible single instruction. This eliminates the need for interrupt masking at the AIC
or Core level in real-time and multi-tasking systems.
An on-chip, 8-channel Peripheral Data Controller (PDC) transfers data between the on-
chip USARTs/SPI and the on and off-chip memories without processor intervention.
One PDC channel is connected to the receiving channel and one to the transmitting
channel of each USART and SPI.
The user interface of a PDC channel is integrated in the memory space of each periph-
eral. It contains a 32-bit address pointer register and a 16-bit count register. When the
programmed data is transferred, an end of transfer interrupt is generated by the corre-
sponding peripheral.
Most importantly, the PDC removes the processor interrupt handling overhead and sig-
nificantly reduces the number of clock cycles required for a data transfer. It can transfer
up to 64K contiguous bytes. As a result, the performance of the microcontroller is
increased and the power consumption reduced.
Control Register – write only register that triggers a command when a one is written
to the corresponding position at the appropriate address. Writing a zero has no
effect.
Mode Register – read/write register that defines the configuration of the peripheral.
Usually has a value of 0x0 after a reset.
Data Registers – read and/or write register that enables the exchange of data
between the processor and the peripheral.
Status Register – read only register that returns the status of the peripheral.
Enable/Disable/Status Registers – shadow command registers. Writing a one in the
Enable Register sets the corresponding bit in the Status Register. Writing a one in
the Disable Register resets the corresponding bit and the result can be read in the
Status Register. Writing a bit to zero has no effect. This register access method
maximizes the efficiency of bit manipulation, and enables modification of a register
with a single non-interruptible instruction, replacing the costly read-modify-write
operation.
1745CS–ATARM–05/02