ATMEGA161-8AI Atmel, ATMEGA161-8AI Datasheet - Page 75

• Manufacturer Part Number: ATMEGA161-8AI
• Description: IC AVR MCU 16K 8MHZ IND 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618AI

UART0 Control and Status
Registers – UCSR0B
UART1 Control and Status
Registers – UCSR1B
1228D–AVR–02/07
• Bit 2
This bit is reserved bit in the ATmega161 and will always read as zero.
• Bit 1
When this bit is set (one), the UART speed will be doubled. This means that a bit will be
transmitted/received in 8 CPU clock periods instead of 16 CPU clock periods. For a
detailed description, see “Double-speed Transmission” on page 78.
• Bit 0
This bit is used to enter Multi-processor Communication mode. The bit is set when the
Slave MCU waits for an address byte to be received. When the MCU has been
addressed, the MCU switches off the MPCMn bit and starts data reception.
For a detailed description, see “Multi-processor Communication mode”.
• Bit 7
When this bit is set (one), a setting of the RXCn bit in UCSRnA will cause the Receive
Complete interrupt routine to be executed, provided that global interrupts are enabled.
• Bit 6
When this bit is set (one), a setting of the TXCn bit in UCSRnA will cause the Transmit
Complete interrupt routine to be executed, provided that global interrupts are enabled.
• Bit 5
When this bit is set (one), a setting of the UDREn bit in UCSRnA will cause the UART
Data Register Empty interrupt routine to be executed, provided that global interrupts are
enabled.
• Bit 4
This bit enables the UART Receiver when set (one). When the Receiver is disabled, the
TXCn, ORn and FEn Status Flags cannot become set. If these flags are set, turning off
RXEN does not cause them to be cleared.
• Bit 3
This bit enables the UART Transmitter when set (one). When disabling the Transmitter
while transmitting a character, the Transmitter is not disabled before the character in the
Shift Register plus any following character in UDRn has been completely transmitted.
Bit
$0A ($2A)
Read/Write
Initial Value
Bit
$01 ($21)
Read/Write
Initial Value
–
–
–
–
–
–
–
–
Res: Reserved Bit
U2X0/U2X1: Double the UART Transmission Speed
MPCM0/MPCM1: Multi-processor Communication Mode
RXCIE0/RXCIE1: RX Complete Interrupt Enable
TXCIE0/TXCIE1: TX Complete Interrupt Enable
UDRIE0/UDREI1: UART Data Register Empty Interrupt Enable
RXEN0/RXEN1: Receiver Enable
TXEN0/TXEN1: Transmitter Enable
RXCIE1
RXCIE0
R/W
R/W
7
0
7
0
TXCIE1
TXCIE0
R/W
R/W
6
0
6
0
UDRIE1
UDRIE0
R/W
R/W
5
0
5
0
RXEN1
RXEN0
R/W
R/W
4
0
4
0
TXEN1
TXEN0
R/W
R/W
3
0
3
0
CHR90
CHR91
R/W
R/W
2
0
2
0
ATmega161(L)
RXB80
RXB81
R
R
1
1
1
1
TXB80
TXB81
R/W
R/W
0
0
0
0
UCSR0B
UCSR1B
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