ATMEGA161L-4AI Atmel, ATMEGA161L-4AI Datasheet - Page 92

• Manufacturer Part Number: ATMEGA161L-4AI
• Description: IC AVR MCU 16K LV 4MZ IND 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA161L4AI

Port B as General Digital I/O
Alternate Functions of Port B
92
ATmega161(L)
All eight pins in Port B have equal functionality when used as digital I/O pins.
PBn, general I/O pin: The DDBn bit in the DDRB Register selects the direction of this
pin. If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero),
PBn is configured as an input pin. If PORTBn is set (one) when the pin is configured as
an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the
PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The
Port B pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
Table 31. DDBn Effects on Port B Pins
Note:
The alternate pin configuration is as follows:
• SCK
SCK: Master clock output, Slave clock input pin for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB7.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB7 bit. See the description of the SPI port for further details.
• MISO
MISO: Master data input, Slave data output pin for SPI channel. When the SPI is
enabled as a master, this pin is configured as an input regardless of the setting of
DDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by
DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB6 bit. See the description of the SPI port for further details.
• MOSI
MOSI: SPI Master data output, Slave data input for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB5 bit. See the description of the SPI port for further details.
• SS
SS: Slave port select input. When the SPI is enabled as a Slave, this pin is configured
as an input regardless of the setting of DDB5. As a Slave, the SPI is activated when this
pin is driven low. When the SPI is enabled as a master, the data direction of this pin is
controlled by DDB5. When the pin is forced to be an input, the pull-up can still be con-
trolled by the PORTB5 bit. See the description of the SPI port for further details.
DDBn
0
0
1
1
–
Port B, Bit 4
–
1. n: 7,6…0, pin number
–
–
Port B, Bit 7
Port B, Bit 6
Port B, Bit 5
PORTBn
0
1
0
1
Output
Output
Input
Input
I/O
Pull-up
Yes
No
No
No
(1)
Comment
Tri-state (high-Z)
PBn will source current if ext. pulled low.
Push-pull Zero Output
Push-pull One Output
1228D–AVR–02/07