ATMEGA8-16AI Atmel, ATMEGA8-16AI Datasheet - Page 119
![IC AVR MCU 8K 16MHZ IND 32-TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA8-16AI
Manufacturer Part Number
ATMEGA8-16AI
Description
IC AVR MCU 8K 16MHZ IND 32-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA816AI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8-16AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Timer/Counter
Interrupt Mask
Register – TIMSK
Timer/Counter
Interrupt Flag Register
– TIFR
2486Z–AVR–02/11
•
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter2 occurs (that is, when the OCF2 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR).
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs (that is, when the TOV2 bit is set in the Timer/Counter Inter-
rupt Flag Register – TIFR).
• Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the
data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the
corresponding interrupt Handling Vector. Alternatively, OCF2 is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and
OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-
ware when executing the corresponding interrupt Handling Vector. Alternatively, TOV2 is
cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow
Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
During asynchronous operation, the synchronization of the Interrupt Flags for the
asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting
of the Interrupt Flag. The Output Compare Pin is changed on the timer clock and is not
synchronized to the processor clock
OCIE2
OCF2
R/W
R/W
7
0
7
0
TOIE2
TOV2
R/W
R/W
6
0
6
0
TICIE1
ICF1
R/W
R/W
5
0
5
0
OCIE1A
OCF1A
R/W
R/W
4
0
4
0
OCIE1B
OCF1B
R/W
R/W
3
0
3
0
TOIE1
TOV1
R/W
R/W
2
0
2
0
R
R
1
–
0
1
–
0
TOIE0
TOV0
R/W
R/W
ATmega8(L)
0
0
0
0
TIMSK
TIFR
119
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