ATMEGA8L-8PI Atmel, ATMEGA8L-8PI Datasheet - Page 131

• Manufacturer Part Number: ATMEGA8L-8PI
• Description: IC AVR MCU 8K LV 8MHZ IND 28-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA8L8PI

Internal Clock
Generation – The
Baud Rate Generator
2486Z–AVR–02/11
Figure 62. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the Synchronous Master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(fosc), is loaded with the UBRR value each time the counter has counted down to zero or when
the UBRRL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the
baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate generator
output is used directly by the Receiver’s clock and data recovery units. However, the recovery
units use a state machine that uses 2, 8, or 16 states depending on mode set by the state of the
UMSEL, U2X and DDR_XCK bits.
Table 52 on page 132
for calculating the UBRR value for each mode of operation using an internally generated clock
source.
txclk
rxclk
xcki
xcko
fosc
DDR_XCK
XCK
Pin
Transmitter clock. (Internal Signal)
Receiver base clock. (Internal Signal)
Input from XCK pin (internal Signal). Used for synchronous slave operation
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation
XTAL pin frequency (System Clock)
xcko
xcki
OSC
Down-Counter
contains equations for calculating the baud rate (in bits per second) and
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/ 2
Figure
62.
/ 4
/ 2
DDR_XCK
ATmega8(L)
U2X
0
1
0
1
0
1
1
0
UMSEL
txclk
rxclk
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