ATMEGA8L-8PI Atmel, ATMEGA8L-8PI Datasheet - Page 133

• Manufacturer Part Number: ATMEGA8L-8PI
• Description: IC AVR MCU 8K LV 8MHZ IND 28-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA8L8PI

Frame Formats
2486Z–AVR–02/11
Figure 63. Synchronous Mode XCK Timing
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is
used for data change. As
ing XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at
falling XCK edge and sampled at rising XCK edge.
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
•
•
•
•
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 64
optional.
Figure 64. Frame Formats
The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB
and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting
of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
St
(n)
P
Sp
IDLE
1 start bit
5, 6, 7, 8, or 9 data bits
no, even or odd parity bit
1 or 2 stop bits
UCPOL = 1
UCPOL = 0
Start bit, always low
Data bits (0 to 8)
Parity bit. Can be odd or even
Stop bit, always high
No transfers on the communication line (RxD or TxD). An IDLE line must be high
illustrates the possible combinations of the frame formats. Bits inside brackets are
(IDLE)
RxD / TxD
RxD / TxD
St
XCK
XCK
0
Figure 63
1
2
shows, when UCPOL is zero the data will be changed at ris-
3
4
FRAME
[5]
[6]
[7]
[8]
[P]
Sample
Sample
Sp1 [Sp2]
ATmega8(L)
(St / IDLE)
133