T89C51RD2-SLSIM Atmel, T89C51RD2-SLSIM Datasheet - Page 49
![IC MICRO CTRL 64K FLASH 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
T89C51RD2-SLSIM
Manufacturer Part Number
T89C51RD2-SLSIM
Description
IC MICRO CTRL 64K FLASH 44PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.T89C51RD2-SMSIM.pdf
(104 pages)
Specifications of T89C51RD2-SLSIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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Reduced EMI Mode
4243G–8051–05/03
The ALE signal is used to demultiplex address and data buses on port 0 when used with
external program or data memory. Nevertheless, during internal code execution, ALE
signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting
AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no
longer output but remains active during MOVX and MOVC instructions and external
fetches. During ALE disabling, ALE pin is weakly pulled high.
Table 31. AUXR Register
AUXR - Auxiliary Register (8Eh)
Reset Value = XX0X 1000b
Not bit addressable
Number
Bit
7
6
5
4
3
2
1
0
7
-
Mnemonic
EXTRAM
XRS1
XRS0
Bit
M0
AO
6
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
M0 bit: Pulse length in clock period
Stretch MOVX control: the RD/ and the WR/ pulse length is increased
according to the value of M0. see table 6
Reserved
The value read from this bit is indeterminate. Do not set this bit.
XRS1 bit
XRAM size: Accessible size of the XRAM. See Table 6.
XRS0 bit
XRAM size: Accessible size of the XRAM. Table 6.
EXTRAM bit
See Table 6.
ALE Output bit
Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.
M0
5
4
-
XRS1
3
Description
XRS0
2
T89C51RD2
EXTRAM
1
AO
0
49
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