ATMEGA162-16PC Atmel, ATMEGA162-16PC Datasheet - Page 83

• Manufacturer Part Number: ATMEGA162-16PC
• Description: IC MCU AVR 16K 5V 16MHZ 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Extended MCU Control
Register – EMCUCR
2513C–AVR–09/02
Table 43. Interrupt 1 Sense Control
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask are set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 44. The value on the INT0 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer
than one clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. If low level interrupt is selected, the low level must be held until
the completion of the currently executing instruction to generate an interrupt.
Table 44. Interrupt 0 Sense Control
• Bit 0 – ISC2: Interrupt Sense Control 2
The asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG
I-bit and the corresponding interrupt mask in GICR are set. If ISC2 is cleared (zero), a
falling edge on INT2 activates the interrupt. If ISC2 is set (one), a rising edge on INT2
activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on INT2
wider than the minimum pulse width given in Table 45 will generate an interrupt. Shorter
pulses are not guaranteed to generate an interrupt. When changing the ISC2 bit, an
interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing its
Interrupt Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally,
the INT2 interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit
(INTF2) in the GIFR Register before the interrupt is re-enabled.
Table 45. Asynchronous External Interrupt Characteristics
Bit
Read/Write
Initial Value
Symbol
ISC11
ISC01
t
INT
0
0
1
1
0
0
1
1
Parameter
Minimum pulse width for
asynchronous external interrupt
ISC10
ISC00
0
1
0
1
0
1
0
1
SM0
R/W
7
0
Description
The low level of INT1 generates an interrupt request.
Any logical change on INT1 generates an interrupt request.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
SRL2
R/W
6
0
SRL1
R/W
5
0
SRL0
R/W
4
0
SRW01
R/W
Condition
3
0
ATmega162(V/U/L)
SRW00
R/W
2
0
Min.
SRW11
R/W
1
0
Typ.
50
ISC2
R/W
0
0
Max.
EMCUCR
Units
ns
83