ATMEGA162-16AC Atmel, ATMEGA162-16AC Datasheet
ATMEGA162-16AC
Specifications of ATMEGA162-16AC
Related parts for ATMEGA162-16AC
ATMEGA162-16AC Summary of contents
Page 1
... ATmega162V – 2.4 - 4.0V for ATmega162U – 2.7 - 5.5V for ATmega162L – 4.5 - 5.5V for ATmega162 • Speed Grades – MHz for ATmega162V – MHz for ATmega162L/U – MHz for ATmega162 ® 8-bit Microcontroller 8-bit ATmega162 ATmega162V ATmega162U ATmega162L ...
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... Pin Configurations Disclaimer ATmega162(V/U/L) 2 Figure 1. Pinout ATmega162 (OC0/T0) PB0 (OC2/T1) PB1 (RXD1/AIN0) PB2 (TXD1/AIN1) PB3 (SS/OC3B) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD0) PD0 (TXD0) PD1 (INT0/XCK1) PD2 (INT1/ICP3) PD3 (TOSC1/XCK0/OC3A) PD4 (OC1A/TOSC2) PD5 (WR) PD6 (RD) PD7 XTAL2 XTAL1 (MOSI) PB5 ...
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... Overview Block Diagram 2513C–AVR–09/02 The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the sys- tem designer to optimize power consumption versus processing speed. ...
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... ATmega161, all I/O locations present in ATmega161 have the same locations in ATmega162. Some additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF, (i.e., in the ATmega162 internal RAM space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions ...
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... The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega162 as listed on page 70. Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
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... The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega162 as listed on page 79. Reset input. A low level on this pin for longer than the minimum pulse length will gener- ate a Reset, even if the clock is not running ...
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... This allows single-cycle Arithmetic Logic Unit (ALU) operation typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. ATmega162(V/U/L) Data Bus 8-bit Status and Control ...
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... ALU – Arithmetic Logic Unit Status Register ATmega162(V/U/L) 8 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Pro- gram memory ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc- tion Set Description” for detailed information. ATmega162(V/U/ ...
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... General Purpose Register File ATmega162(V/U/L) 10 The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • ...
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... AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit SP15 SP14 SP13 SP7 SP6 SP5 Read/Write R/W R/W R/W R/W R/W R/W Initial Value ATmega162(V/U/ R26 (0x1A R28 (0x1C R30 (0x1E SP12 SP11 SP10 SP9 SP4 SP3 SP2 SP1 4 ...
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... Instruction Execution Timing Reset and Interrupt Handling ATmega162(V/U/L) 12 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept ...
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... EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ ATmega162(V/U/L) 13 ...
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... Interrupt Response Time ATmega162(V/U/L) 14 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set global interrupt enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ...
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... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega162 Program Counter (PC bits wide, thus addressing the 8K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “ ...
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... Register File and I/O Memory, and the next 1024 locations address the internal data SRAM. An optional external data SRAM can be used with the ATmega162. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 (+160) I/O Registers, and the 1024 bytes of internal data SRAM in the ATmega162 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10. ...
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... Register – EEARH and EEARL ATmega162(V/U/L) 18 The ATmega162 contains 512 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega162 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. • ...
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... ATmega162(V/U/L) 20 can be omitted. See “Boot Loader Support – Read-While-Write Self-programming” on page 214 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail ...
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... EEPROM_write(unsigned int uiAddress, unsigned char ucData Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } ATmega162(V/U/L) 21 ...
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... Preventing EEPROM Corruption ATmega162(V/U/L) 22 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ...
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... The I/O space definition of the ATmega162 is shown in “Register Summary” on page 272. All ATmega162 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... External Memory Interface Overview Using the External Memory Interface ATmega162(V/U/L) 24 With all the features the External Memory Interface provides well suited to operate as an interface to memory devices such as external SRAM and FLASH, and peripherals such as LCD-display, A/D, and D/A. The main features are: • ...
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... The data setup time before G low (t ) must not exceed address valid to ALE low (t su delay (dependent on the capacitive load). Figure 12. External SRAM Connected to the AVR AD7:0 ALE AVR A15 ATmega162(V/U/ Table 116 to Table 123 on LAXX_LD LLAXX_ST ) must be taken into consideration when pd ) minus PCB wiring ...
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... The most important parameters are the access time for the external memory in conjunction with the set-up requirement of the ATmega162. The access time for the external memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus ...
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... Prev. data Address DA7:0 (XMBK = 1) RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external). ATmega162(V/U/ Address Address XX Data Address ...
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... XMEM Register Description MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR ATmega162(V/U/L) 28 Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = System Clock (CLK ) CPU ALE A15:8 Prev. addr. DA7:0 Prev. data Address XX WR DA7:0 (XMBK = 0) Address DA7:0 (XMBK = 1) Prev ...
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... Note (lower/upper sector). For further details of the timing and wait-states of the External Memory Interface, see Figure 13 to Figure 16 how the setting of the SRW bits affects the timing. ATmega162(V/U/L) Sector Limits Lower sector = N/A Upper sector = 0x1100 - 0xFFFF Lower sector = 0x1100 - 0x1FFF ...
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... Special Function IO Register – SFIOR Using all Locations of External Memory Smaller than 64 KB ATmega162(V/U/L) 30 Bit TSM XMBK XMM2 Read/Write R/W R/W R/W Initial Value • Bit 6 – XMBK: External Memory Bus Keeper Enable Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-stated the lines ...
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... KB memory will appear as one linear 32 KB address space from 0x0460 to 0x845F. External 32K SRAM 0x0000 0x0000 0x045F 0x0460 0x04FF 0x0500 0x7FFF 0x7FFF 0x8000 0x845F 0x8460 0xFFFF ATmega162(V/U/L) Memory Configuration B AVR Memory Map External 32K SRAM Internal Memory External Memory (Unused) 0x0000 0x045F 0x0460 0x7FFF 31 ...
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... Using all 64KB Locations of External Memory ATmega162(V/U/L) 32 Since the external memory is mapped after the internal memory as shown in Figure 11, only 64,256 Bytes of external memory are available by default (address space 0x0000 to 0x05FF is reserved for internal memory). However possible to take advantage of the entire external memory by masking the higher address bits to zero. This can be done by using the XMMn bits and control by software the most significant bits of the address ...
Page 33
... CPU clock. The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a realtime counter even when the device is in sleep mode. ATmega162(V/U/L) CPU Core RAM clk ...
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... The number of WDT Oscillator cycles used for each Time-out is shown in Table 6. The frequency of the Watchdog Oscillator is voltage dependent as shown in “ATmega162 Typical Characteristics – Pre- liminary Data” on page 271. Table 6. Number of Watchdog Oscillator Cycles Typ Time-out ( ...
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... Table 8. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and CKSEL0 SUT1:0 Power-save 0 00 258 258 ATmega162(V/U/L) XTAL2 XTAL1 GND Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – Additional Delay from Reset (V = 5.0V) CC (1) 4 (2) – (2) 4 ...
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... Low-frequency Crystal Oscillator ATmega162(V/U/L) 36 Table 8. Start-up Times for the Crystal Oscillator Clock Selection (Continued) Start-up Time from Power-down and CKSEL0 SUT1:0 Power-save 1 01 16K 16K 16K CK Notes: 1. These options should only be used when not operating close to the maximum fre- quency of the device, and only if frequency stability at start-up is not important for the application ...
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... The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not cali- brate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. ATmega162(V/U/L) Nominal Frequency 8.0 MHz Additional Delay from Reset ( ...
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... External Clock ATmega162(V/U/L) 38 Table 13. Internal RC Oscillator Frequency Range. Min Frequency in Percentage of OSCCAL Value Nominal Frequency 0x00 50% 0x3F 75% 0x7F 100% 0x80 - 0xFF To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 20. To run the device on an external clock, the CKSEL Fuses must be pro- grammed to “ ...
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... Applying an external clock source to TOSC1 is not recommended. The ATmega162 system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the require- ment for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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... ATmega162(V/U/L) 40 The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro- grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0100”, giving a division factor start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions ...
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... If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 18 on page 33 presents the different clock systems in the ATmega162, and their distribution. The figure is helpful in selecting an appropriate sleep mode. ...
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... Extended MCU Control Register – EMCUCR Idle Mode Power-down Mode ATmega162(V/U/L) 42 Bit SM0 SRL2 SRL1 Read/Write R/W R/W R/W Initial Value • Bit 7 – SM0: Sleep Mode Select Bit 0 The Sleep Mode Select bits select between the five available sleep modes as shown in Table 16 ...
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... Power-save mode with the exception that the main Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. Oscillators Main Clock clk clk Source Enabled IO ASY ( ( ATmega162(V/U/L) , allowing operation only of asyn- ASY Wake-up Sources INT2 INT1 Timer Osc INT0 Enabled and Pin Change Timer ( (3) X (2) (3) ...
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... Internal Voltage Reference Watchdog Timer Port Pins On-chip Debug System ATmega162(V/U/L) 44 There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possi- ble, and the sleep mode should be selected so that as few as possible of the device’s functions are operating ...
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... The Time-out period of the delay counter is defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 34. The ATmega162 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ) ...
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... Power-on Reset ATmega162(V/U/L) 46 Figure 21. Reset Logic V CC BODLEVEL [ 2..0] Pull-up Resistor SPIKE RESET FILTER JTAG Reset Register CKSEL[3:0] Table 18. Reset Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT Power-on Reset Threshold Voltage (1) (falling) V RESET Pin Threshold Voltage RST t Minimum pulse width on RESET Pin ...
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... Table 18) will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset. When the applied signal reaches the Reset Threshold Voltage – V counter starts the MCU after the Time-out period t Figure 24. External Reset During Operation CC ATmega162(V/U/ RST t ...
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... This guarantees that a Brown-out Reset will occour before voltage where correct operation of the microcontroller is no longer guarateed. This test is performed using BODLEVEL = 110 for ATmega162V, BODLEVEL = 101 for ATmega162L, and BODLEVEL = 100 for ATmega162. 2. BODLEVEL = 011 for ATmega162U. Otherwise reserved. ...
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... JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. ATmega162(V/U/L) V BOT+ t TOUT ...
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... Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega162 resets and executes from the Reset Vector. For tim- ing details on the Watchdog Reset, refer to page 52. ...
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... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega162 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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... ATmega162(V/U/ the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow- ing procedure must be followed the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. ...
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... WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret C Code Example void WDT_off(void Write logical one to WDCE and WDE */ WDTCR = (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; } ATmega162(V/U/L) 53 ...
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... Configuration of the Watchdog Timer Safety Level 0 Safety Level 1 Safety Level 2 ATmega162(V/U/L) 54 The sequence for changing configuration differs slightly between the three safety levels. Separate procedures are described for each level. This mode is compatible with the Watchdog operation found in ATmega161. The Watch- dog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any restriction ...
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... This section describes the specifics of the interrupt handling as performed in ATmega162. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Table 24 shows the interrupt table when the com- patibility fuse (M161C) is unprogrammed, while Table 25 shows the interrupt table when M161C Fuse is programmed ...
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... ATmega162(V/U/L) 56 Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot Loader Support – Read-While-Write Self-programming” on page 214. 2. When the IVSEL bit in GICR is set, Interrupt Vectors will be moved to the start of the Boot Flash section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash section ...
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... Note: 1. The Boot Reset Address is shown in Table 94 on page 226. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega162 is: Address Labels Code ...
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... ATmega162(V/U/L) 58 0x03A ldi r16,low(RAMEND) 0x03B out SPL,r16 0x03C sei 0x03D <instr> ... ... ... When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ...
Page 59
... Boot Lock bits. • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the ATmega162(V/U/L) Comments ; Reset handler ; IRQ0 Handler ...
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... ATmega162(V/U/L) 60 IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ...
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... Port Functions” on page 66. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATmega162(V/U/ Logic See figure " ...
Page 62
... Ports as General Digital I/O Configuring the Pin ATmega162(V/U/L) 62 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 29 shows a functional description of one I/O-port pin, here generically called Pxn. (1) Figure 29. General Digital I/O Pxn PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clk ...
Page 63
... The maximum and minimum propagation delays are denoted t respectively. Figure 30. Synchronization when Reading an Externally Applied Pin Value SYSTEM CLK INSTRUCTIONS XXX SYNC LATCH PINxn r17 ATmega162(V/U/L) I/O Pull-up Comment Input No Tri-state (Hi-Z) Pxn will source current if ext. pulled Input Yes low ...
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... ATmega162(V/U/L) 64 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low ...
Page 65
... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. ATmega162(V/U/L) / ...
Page 66
... Unconnected pins Alternate Port Functions ATmega162(V/U/ some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). ...
Page 67
... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega162(V/U/L) Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010 ...
Page 68
... Special Function IO Register – SFIOR Alternate Functions of Port A ATmega162(V/U/L) 68 Bit TSM XMBK XMM2 Read/Write R/W R/W R/W Initial Value • Bit 2 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). ...
Page 69
... PCIE0 • PCINT2 DIEOV INPUT D2 INPUT /PCINT3 /PCINT2 AIO – – Notes: 1. PCINT is Pin Change Interrupt Enable bit n. 2. PCINT is Pin Change Interrupt input n. ATmega162(V/U/L) PA5/AD5/PCINT5 SRE ~(WR + ADA) • PORTA5 SRE WR + ADA SRE if (ADA) then A6 A5 else D6 OUTPUT D5 OUTPUT • WR • WR PCIE0 • ...
Page 70
... Alternate Functions Of Port B ATmega162(V/U/L) 70 The Port B pins with alternate functions are shown in Table 32. Table 32. Port B Pins Alternate Functions Port Pin Alternate Functions PB7 SCK (SPI Bus Serial Clock) PB6 MISO (SPI Bus Master Input/Slave Output) PB5 MOSI (SPI Bus Master Output/Slave Input) ...
Page 71
... PORTB0 and DDB0 settings. It will also be output during reset. Table 33 and Table 34 relate the alternate functions of Port B to the overriding signals shown in Figure 32 on page 66. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. ATmega162(V/U/L) 71 ...
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... ATmega162(V/U/L) 72 Table 33. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/SCK PB6/MISO PUOE SPE • MSTR SPE • MSTR PUOV PORTB7 • PORTB6 • PUD PUD DDOE SPE • MSTR SPE • MSTR DDOV 0 0 PVOE SPE • MSTR SPE • MSTR ...
Page 73
... A14, External memory interface address bit 14. TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Regis- ter. When the JTAG interface is enabled, this pin can not be used as an I/O pin. PCINT14: The pin can also serve as a pin change interrupt. ATmega162(V/U/L) 73 ...
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... ATmega162(V/U/L) 74 • A13/TMS/PCINT13 – Port C, Bit 5 A13, External memory interface address bit 13. TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. PCINT13: The pin can also serve as a pin change interrupt. ...
Page 75
... PCIE1 • PCINT11 DIEOV 1 (2) DI PCINT11 AIO – Notes: 1. PCINTn is Pin Change Interrupt Enable bit n. 2. PCINTn is Pin Change Interrupt input n. ATmega162(V/U/L) PC6/A14/TDO PC5/A13/TMS /PCINT14 /PCINT13 (XMM < 2) • (XMM < 3) • SRE +JTAGEN SRE + JTAGEN 0 JTAGEN SRE • (XMM<2) SRE • (XMM<3) ...
Page 76
... Alternate Functions of Port D ATmega162(V/U/L) 76 The Port D pins with alternate functions are shown in Table 38. Table 38. Port D Pins Alternate Functions Port Pin Alternate Function PD7 RD (Read strobe to external memory) PD6 WR (Write strobe to external memory) TOSC2 (Timer Oscillator Pin 2) PD5 OC1A (Timer/Counter1 Output Compare A Match Output) ...
Page 77
... The XCK1 pin is active only when USART1 operates in Synchronous mode. • TXD0 – Port D, Bit 1 TXD0, Transmit Data (Data output pin for USART0). When the USART0 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1. ATmega162(V/U/L) 77 ...
Page 78
... ATmega162(V/U/L) 78 • RXD0 – Port D, Bit 0 RXD0, Receive Data (Data input pin for USART0). When the USART0 Receiver is enabled this pin is configured as an input regardless of the value of DDD0. When USART0 forces this pin input, the pull-up can still be controlled by the PORTD0 bit ...
Page 79
... Table 42. Overriding Signals for Alternate Functions PE2..PE0 Signal Name PE2 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE OC1B ENABLE PVOV OC1B DIEOE 0 DIEOV AIO – ATmega162(V/U/L) PE1 PE0 SRE SRE SRE 0 ALE 0 0 INT2 ENABLED INT2 INPUT/ ICP1 INPUT – – 79 ...
Page 80
... Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port C Data Register – PORTC Port C Data Direction Register – DDRC ATmega162(V/U/L) 80 Bit PORTA7 PORTA6 PORTA5 Read/Write R/W ...
Page 81
... Read/Write Initial Value Bit – – – Read/Write Initial Value Bit – – – Read/Write Initial Value ATmega162(V/U/ PINC4 PINC3 PINC2 PINC1 N/A N/A N/A N PORTD4 PORTD3 PORTD2 PORTD1 R/W R/W R/W R DDD4 DDD3 DDD2 DDD1 R/W R/W ...
Page 82
... External Interrupts MCU Control Register – MCUCR ATmega162(V/U/L) 82 The External Interrupts are triggered by the INT0, INT1, INT2 pin, or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2..0 or PCINT15..0 pins are configured as outputs. This feature provides a way of generating a software interrupt ...
Page 83
... INT2 interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTF2) in the GIFR Register before the interrupt is re-enabled. Table 45. Asynchronous External Interrupt Characteristics Symbol Parameter Minimum pulse width for t INT asynchronous external interrupt ATmega162(V/U/ SRL0 SRW01 SRW00 SRW11 ...
Page 84
... General Interrupt Control Register – GICR ATmega162(V/U/L) 84 Bit INT1 INT0 INT2 Read/Write R/W R/W R/W Initial Value • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed ...
Page 85
... If the I-bit in SREG and the PCIE0 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter- rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. ATmega162(V/U/ ...
Page 86
... Pin Change Mask Register 1 – PCMSK1 Pin Change Mask Register 0 – PCMSK0 ATmega162(V/U/L) 86 Bit PCINT15 PCINT14 PCINT13 Read/Write R/W R/W R/W Initial Value • Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8 Each PCINT15..8 bit selects whether pin change interrupt is enabled on the correspond- ing I/O pin ...
Page 87
... Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 33. For the actual placement of I/O pins, refer to “Pinout ATmega162” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 88
... Definitions Timer/Counter Clock Sources ATmega162(V/U/L) 88 inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clk T The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Wave- form Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0). See “ ...
Page 89
... WGM01:0 bits and Compare Output mode (COM01:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 92.). ATmega162(V/U/L) TOVn (Int.Req.) Clock Select ...
Page 90
... Force Output Compare Compare Match Blocking by TCNT0 Write ATmega162(V/U/L) 90 Figure 35 shows a block diagram of the output compare unit. Figure 35. Output Compare Unit, Block Diagram OCRn top bottom Waveform Generator FOCn WGMn1:0 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes ...
Page 91
... Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0 pin (DDR_OC0) must be set as output before the OC0 value is visible on the pin. The port override function is independent of the Waveform Generation mode. ATmega162(V/U/ ...
Page 92
... Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega162(V/U/L) 92 The design of the output compare pin logic allows initialization of the OC0 state before the output is enabled. Note that some COM01:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 98. ...
Page 93
... The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 38. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes ATmega162(V/U/L) OCn Interrupt Flag Set 2 ...
Page 94
... ATmega162(V/U/L) 94 non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0. Figure 38. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value ...
Page 95
... The PWM waveform is generated by clearing (or setting) the OC0 Register at the compare match between OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0 Register at compare match between ATmega162(V/U/L) OCn Interrupt Flag Set OCRn Update ...
Page 96
... Timer/Counter Timing Diagrams ATmega162(V/U/L) 96 OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode ...
Page 97
... Figure 43 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. Figure 43. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRn OCFn ATmega162(V/U/L) OCRn OCRn + 1 OCRn Value TOP BOTTOM TOP /8) clk_I/O OCRn + 2 BOTTOM + 1 97 ...
Page 98
... Timer/Counter Register Description Timer/Counter Control Register – TCCR0 ATmega162(V/U/L) 98 Bit FOC0 WGM00 COM01 Read/Write W R/W R/W Initial Value • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode ...
Page 99
... Set OC0 on compare match when up-counting. Clear OC0 on compare match when downcounting. Note special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 95 for more details. ATmega162(V/U/L) (1) (1) 99 ...
Page 100
... Timer/Counter Register – TCNT0 Output Compare Register – OCR0 Timer/Counter Interrupt Mask Register – TIMSK ATmega162(V/U/L) 100 • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 51. Clock Select Bit Description CS02 ...
Page 101
... OCR0 – Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Com- pare match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed. ATmega162(V/U/ ...
Page 102
... Timer/Counter3 Prescalers Internal Clock Source Prescaler Reset External Clock Source ATmega162(V/U/L) 102 Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler mod- ule, but the Timer/Counters can have different prescaler settings. The description below applies to Timer/Counter3, Timer/Counter1, and Timer/Counter0. The Timer/Counter can be clocked directly by the system clock (by setting the CSn2 ...
Page 103
... This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect all three timers. ATmega162(V/U/L) < f /2) given a 50/50% duty cycle. Since ExtClk clk_I/O /2 ...
Page 104
... A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 46. For the actual placement of I/O pins, refer to “Pinout ATmega162” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” ...
Page 105
... Timer Clock (clk The double buffered Output Compare Registers (OCRnA/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare pin ATmega162(V/U/L) (1) TOVn (Int.Req.) ...
Page 106
... Definitions Compatibility ATmega162(V/U/L) 106 (OCnA/B). See “Output Compare Units” on page 113. The compare match event will also set the Compare Match Flag (OCFnA/B) which can be used to generate an output compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn the Analog Compar- ator pins (See “ ...
Page 107
... It is important to notice that accessing 16-bit registers are atomic operations inter- rupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted. ATmega162(V/U/L) 107 ...
Page 108
... ATmega162(V/U/L) 108 Therefore, when both the main code and the interrupt code update the temporary regis- ter, the main code must disable the interrupts during the 16-bit access. The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnA/B or ICRn Registers can be done by using the same principle ...
Page 109
... If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATmega162(V/U/L) 109 ...
Page 110
... Timer/Counter Clock Sources Counter Unit ATmega162(V/U/L) 110 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter Control Register B (TCCRnB). For details “ /Cou nte r0, Tim er /Co unt Timer/Counter3 Prescalers” ...
Page 111
... ICRn Register. If enabled (TICIEn = 1), the input capture flag generates an input capture interrupt. The ICFn flag is automatically cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by writing a logical one to its I/O bit location. ATmega162(V/U/L) (1) DATA BUS (8-bit) TCNTnH (8-bit) ...
Page 112
... Input Capture Trigger Source Noise Canceler Using the Input Capture Unit ATmega162(V/U/L) 112 Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte temporary register (TEMP) ...
Page 113
... The OCRnx Register is double buffered when using any of the twelve Pulse Width Mod- ulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting ATmega162(V/U/L) DATA BUS (8-bit) OCRnxL Buf. (8-bit) ...
Page 114
... Compare Match Blocking by TCNTn Write Using the Output Compare Unit ATmega162(V/U/L) 114 sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx directly ...
Page 115
... The design of the output compare pin logic allows initialization of the OCnx state before the output is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation. See “16-bit Timer/Counter Register Description” on page 126. The COMnx1:0 bits have no effect on the input capture unit. ATmega162(V/U/ ...
Page 116
... Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega162(V/U/L) 116 The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1 tells the Waveform Generator that no action on the OCnx Register performed on the next compare match. For Com- pare Output actions in the non-PWM modes refer to Table 53 on page 126 ...
Page 117
... The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). For Timer/Counter3 also prescaler factors 16 and 32 are available. As for the Normal mode of operation, the TOVn flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. ATmega162(V/U/L) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) ...
Page 118
... Fast PWM Mode ATmega162(V/U/L) 118 The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5,6,7,14, or 15) pro- vides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM ...
Page 119
... OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). The waveform generated will have a maximum frequency of f set to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. ATmega162(V/U/L) f clk_I/O = ...
Page 120
... Phase Correct PWM Mode ATmega162(V/U/L) 120 The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM ...
Page 121
... TOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the compare match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency com- ATmega162(V/U/L) f clk_I/O = ...
Page 122
... ATmega162(V/U/L) 122 pared to the single-slope operation. However, due to the symmetric feature of the dual- slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see Figure 53 and Figure 54) ...
Page 123
... PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. ATmega162(V/U/L) f clk_I/O = ...
Page 124
... Timer/Counter Timing Diagrams ATmega162(V/U/L) 124 The Timer/Counter is a synchronous design and the timer clock (clk shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 55 shows a timing diagram for the setting of OCFnx ...
Page 125
... I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) ATmega162(V/U/L) TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 ...
Page 126
... Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Timer/Counter3 Control Register A – TCCR3A ATmega162(V/U/L) 126 Bit COM1A1 COM1A0 COM1B1 Read/Write R/W R/W R/W Initial Value Bit COM3A1 COM3A0 COM3B1 Read/Write R/W R/W R/W Initial Value • Bit 7:6 – COMnA1:0: Compare Output Mode for channel A • ...
Page 127
... COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. ATmega162(V/U/L) (1) 127 ...
Page 128
... Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega162(V/U/L) 128 • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 56 ...
Page 129
... Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written. • Bit 4:3 – WGMn3:2: Waveform Generation Mode See TCCRnA Register description. ATmega162(V/U/ WGM13 ...
Page 130
... ATmega162(V/U/L) 130 • Bit 2:0 – CSn2:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 55 and Figure 56. Table 57. Clock Select Bit Description Timer/Counter1 CS12 CS11 CS10 Description clock source. (Timer/Counter stopped clk ...
Page 131
... Initial Value Bit Read/Write R/W R/W R/W Initial Value Bit Read/Write R/W R/W R/W Initial Value Bit Read/Write R/W R/W R/W Initial Value ATmega162(V/U/ TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R/W R TCNT3[15:8] TCNT3[7:0] R/W R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W ...
Page 132
... Input Capture Register 3 – ICR3H and ICR3L Timer/Counter Interrupt Mask (1) Register – TIMSK ATmega162(V/U/L) 132 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNTn). A match can be used to generate an output compare interrupt generate a waveform output on the OCnx pin. ...
Page 133
... Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo- bally enabled), the Timer/Counter3 overflow interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 55.) is executed when the TOV3 flag, located in TIFR, is set. ATmega162(V/U/ ...
Page 134
... Timer/Counter Interrupt Flag (1) Register – TIFR ATmega162(V/U/L) 134 Bit TOV1 OCF1A OC1FB Read/Write R/W R/W R/W Initial Value Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective Timer sections. • ...
Page 135
... TOV3 flag is set when the timer overflows. Refer to Table 56 on page 128 for the TOV3 flag behavior when using another WGMn3:0 bit setting. TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt Vector is executed. Alternatively, TOV3 can be cleared by writing a logic one to its bit location. ATmega162(V/U/ ...
Page 136
... Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 59. For the actual placement of I/O pins, refer to “Pinout ATmega162” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 137
... When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asynchronous Status Register – ASSR” on page 150. For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 154. ATmega162(V/U/L) 2 default equal to the MCU clock, clk T ...
Page 138
... Counter Unit Output Compare Unit ATmega162(V/U/L) 138 The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 60 shows a block diagram of the counter and its surrounding environment. Figure 60. Counter Unit Block Diagram DATA BUS count clear TCNTn Control Logic direction ...
Page 139
... Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the output compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the compare match will be missed, ATmega162(V/U/L) DATA BUS TCNTn = (8-bit Comparator ) OCFn (Int ...
Page 140
... Compare Match Output Unit ATmega162(V/U/L) 140 resulting in incorrect Waveform Generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The Setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit in Normal mode ...
Page 141
... The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. ATmega162(V/U/L) 141 ...
Page 142
... Clear Timer on Compare Match (CTC) Mode ATmega162(V/U/L) 142 In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its resolution ...
Page 143
... The PWM waveform is generated by setting (or clearing) the OC2 Register at the compare match between OCR2 and TCNT2, and clearing (or set- ting) the OC2 Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). ATmega162(V/U/L) OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set ...
Page 144
... Phase Correct PWM Mode ATmega162(V/U/L) 144 The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle ...
Page 145
... PWM mode. Figure 66. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn MAX - 1 TOVn Figure 67 shows the same timing data, but with the prescaler enabled. ATmega162(V/U/ set each time the counter reaches BOT- TOV2 f clk_I/O = ----------------- - OCnPCPWM N 510 MAX BOTTOM should I/O ...
Page 146
... ATmega162(V/U/L) 146 Figure 67. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 68 shows the setting of OCF2 in all modes except CTC mode. Figure 68. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 ...
Page 147
... CTC Fast PWM Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def- initions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega162(V/U/ COM20 WGM21 CS22 CS21 R/W R/W ...
Page 148
... ATmega162(V/U/L) 148 • Bit 5:4 – COM21:0: Compare Match Output Mode These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corre- sponding to OC2 pin must be set in order to enable the output driver ...
Page 149
... R/W R/W Initial Value The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an output compare interrupt generate a waveform output on the OC2 pin. ATmega162(V/U/L) Description No clock source (Timer/Counter stopped). 2 clk /(No prescaling clk ...
Page 150
... Asynchronous operation of the Timer/Counter Asynchronous Status Register – ASSR ATmega162(V/U/L) 150 Bit – – – Read/Write Initial Value • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin ...
Page 151
... The user is advised to wait for at least one second before using Timer/Counter2 after Power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake- up from Power-down or Standby mode due to unstable clock signal upon start-up, ATmega162(V/U/L) 151 ...
Page 152
... Timer/Counter Interrupt Mask Register – TIMSK ATmega162(V/U/L) 152 no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake up from Power-save or Extended Standby mode when the Timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the Timer is always advanced by at least one before the processor can read the counter value ...
Page 153
... Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. ATmega162(V/U/ ...
Page 154
... Timer/Counter Prescaler Special Function IO Register – SFIOR ATmega162(V/U/L) 154 Figure 70. Prescaler for Timer/Counter2 clk clk I/O T2S Clear TOSC1 AS2 PSR2 CS20 CS21 CS22 The clock source for Timer/Counter2 is named clk the main system I/O clock clk . By setting the AS2 bit in ASSR, Timer/Counter2 is asyn- IO chronously clocked from the TOSC1 pin ...
Page 155
... Serial Peripheral Interface – SPI 2513C–AVR–09/02 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega162 and peripheral devices or between several AVR devices. The ATmega162 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • ...
Page 156
... ATmega162(V/U/L) 156 When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock gener- ator stops, setting the end of transmission flag (SPIF) ...
Page 157
... Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; } Note: 1. The example code assumes that the part specific header file is included. ATmega162(V/U/L) 157 ...
Page 158
... ATmega162(V/U/L) 158 The following code examples show how to initialize the SPI as a slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) ...
Page 159
... When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. • Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. ATmega162(V/U/ ...
Page 160
... ATmega162(V/U/L) 160 • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • ...
Page 161
... WCOL set, and then accessing the SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the ATmega162 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 68) ...
Page 162
... Data Modes ATmega162(V/U/L) 162 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 73 and Figure 74. Data bits are shifted out and latched in on oppo- site edges of the SCK signal, ensuring sufficient time for data signals to stabilize ...
Page 163
... Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode The ATmega162 has two USARTs, USART0 and USART1. The functionality for both USARTs is described below. USART0 and USART1 have different I/O Registers as shown in “Register Summary” on page 272. Note that in ATmega161 compatibility mode, the double buffering of the USART Receive Register is disabled. For details, see “ ...
Page 164
... ATmega162(V/U/L) 164 Figure 75. USART Block Diagram UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA Note: 1. Refer to Figure 1 on page 2, Table 34 on page 72, Table 39 on page 78, and Table 40 on page 78 for USART pin placement. The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver ...
Page 165
... The XCK pin is only active when using synchronous mode. Figure 76 shows a block diagram of the clock generation logic. Figure 76. Clock Generation Logic, Block Diagram UBRR UBRR+1 Prescaling Down-Counter OSC Sync Register xcki XCK xcko Pin DDR_XCK ATmega162(V/U/L) fosc / DDR_XCK Edge Detector UCPOL U2X txclk 1 0 ...
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... Internal Clock Generation – The Baud Rate Generator ATmega162(V/U/L) 166 Signal description: txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation ...
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... The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 77 shows, when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. ATmega162(V/U/L) f OSC ---------- - ...
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... Frame Formats Parity Bit Calculation ATmega162(V/U/L) 168 A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • ...
Page 169
... UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0); } Note: 1. The example code assumes that the part specific header file is included. More advanced initialization routines can be made that include frame format as parame- ters, disable interrupts and so on. However, many applications use a fixed setting of the ATmega162(V/U/L) 169 ...
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... Data Transmission – The USART Transmitter Sending Frames with Data Bit ATmega162(V/U/L) 170 baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine combined with initialization code for other I/O modules. The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the transmitter’ ...
Page 171
... USART Data Register Empty Interrupt will be executed as long as UDRE is set (pro- vided that global interrupts are enabled). UDRE is cleared by writing UDR. When interrupt-driven data transmission is used, the Data Register Empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register ATmega162(V/U/L) 171 ...
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... Parity Generator Disabling the Transmitter Data Reception – The USART Receiver ATmega162(V/U/L) 172 Empty Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXC) flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer ...
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... Get and return received data from buffer */ return UDR; } Note: 1. The example code assumes that the part specific header file is included. The function simply waits for data to be present in the receive buffer by checking the RXC flag, before reading the buffer and returning the value. ATmega162(V/U/L) 173 ...
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... Receiving Frames with 9 Data Bits ATmega162(V/U/L) 174 If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and UPE status flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change ...
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... Error when received. If parity check is not enabled the UPE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 168 and “Parity Checker” on page 176. ATmega162(V/U/L) 175 ...
Page 176
... Asynchronous Data Reception Asynchronous Clock Recovery ATmega162(V/U/L) 176 The Parity Checker is active when the high USART Parity Mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame ...
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... RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the receiver only uses the first stop bit of a frame. Figure 81 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. ATmega162(V/U/L) START ...
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... Asynchronous Operational Range ATmega162(V/U/L) 178 Figure 81. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = Sample (U2X = 1) The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set. ...
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... When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. ATmega162(V/U/L) Recommended Max. (%) Max ...
Page 180
... Using MPCM ATmega162(V/U/L) 180 The Multi-processor Communication mode enables several slave MCUs to receive data from a Master MCU. This is done by first decoding an address frame to find out which MCU has been addressed particular slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received ...
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... UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1); ... Note: 1. The example code assumes that the part specific header file is included. As the code examples illustrate, write accesses of the two registers are relatively unaf- fected of the sharing of I/O location. ATmega162(V/U/L) 181 ...
Page 182
... Read Access ATmega162(V/U/L) 182 Doing a read access to the UBRRH or the UCSRC Register is a more complex opera- tion. However, in most applications rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register contents. If the register location was read in previous sys- tem clock cycle, reading the register in the current clock cycle will return the UCSRC contents ...
Page 183
... Bit 5 – UDRE: USART Data Register Empty The UDRE flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE flag can generate a Data Register Empty interrupt (see description of the UDRIE bit). ATmega162(V/U/ ...
Page 184
... USART Control and Status Register B – UCSRB ATmega162(V/U/L) 184 UDRE is set after a Reset to indicate that the transmitter is ready. • Bit 4 – FE: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. ...
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... Must be read before reading the low bits from UDR. • Bit 0 – TXB8: Transmit Data Bit 8 TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be written before writing the low bits to UDR. ATmega162(V/U/L) 185 ...
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... USART Control and Status (1) Register C – UCSRC ATmega162(V/U/L) 186 Bit URSEL UMSEL UPM1 Read/Write R/W R/W R/W Initial Value Note: 1. The UCSRC Register shares the same I/O location as the UBRRH Register. See the “Accessing UBRRH/ UCSRC Registers” on page 181 section which describes how to access this register. • ...
Page 187
... UBRRH. The URSEL must be zero when writing the UBRRH. • Bit 14:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. ATmega162(V/U/L) UCSZ0 Character Size 0 ...
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... Max. 62.5 kbps 1. UBRR = 0, Error = 0.0% ATmega162(V/U/L) 188 • Bit 11:0 – UBRR11:0: USART Baud Rate Register This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant bits, and the UBRRL contains the eight least significant bits of the USART baud rate ...
Page 189
... ATmega162(V/U/ 7.3728 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0. ...
Page 190
... Max. 0.5 Mbps 1. UBRR = 0, Error = 0.0% ATmega162(V/U/L) 190 11.0592 f = osc U2X = 1 U2X = 0 Error UBRR Error -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% ...
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... Mbps 1.152 Mbps ATmega162(V/U/ 20.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 ...
Page 192
... Analog Comparator Analog Comparator Control and Status Register – ACSR ATmega162(V/U/L) 192 The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function ...
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... Comparator Interrupt on Falling Output Edge Comparator Interrupt on Rising Output Edge. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis- abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. ATmega162(V/U/L) 193 ...
Page 194
... JTAG Interface and On-chip Debug System Features Overview Test Access Port – TAP ATmega162(V/U/L) 194 • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard • Debugger Access to: – All Internal Peripheral Units – Internal and External RAM – ...
Page 195
... INTERFACE INTERNAL FLASH Address SCAN MEMORY Data CHAIN BREAKPOINT UNIT FLOW CONTROL UNIT OCD STATUS AND CONTROL I/O PORT n ATmega162(V/U/L) AVR CPU PC Instruction DIGITAL ANALOG PERIPHERAL PERIPHERIAL UNITS UNITS JTAG / AVR CORE COMMUNICATION INTERFACE Analog inputs Control & Clock lines 195 ...
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... ATmega162(V/U/L) 196 Figure 84. TAP Controller State Diagram 1 Test-Logic-Reset Run-Test/Idle Select-DR Scan Select-IR Scan 0 1 Capture-DR 0 Shift- Exit1-DR 0 Pause- Exit2-DR 1 Update- Capture-IR 0 Shift- Exit1-IR 0 Pause- Exit2-IR 1 Update- 2513C–AVR–09/02 ...
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... TMS high for five TCK clock periods. For detailed information on the JTAG specification, refer to the literature listed in “Bibli- ography” on page 200. A complete description of the Boundary-scan capabilities are given in the section “IEEE 1149.1 (JTAG) Boundary-scan” on page 201. ATmega162(V/U/L) 197 ...
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... Using the On-chip Debug system ATmega162(V/U/L) 198 As shown in Figure 83, the hardware support for On-chip Debugging consists mainly of • A scan chain on the interface between the internal AVR CPU and the internal peripheral units • Break Point unit • Communication interface between the CPU and JTAG system All read or modify/write operations needed for implementing the Debugger are done by applying AVR instructions via the internal AVR CPU Scan Chain ...
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... This is a security feature that ensures no backdoor exists for reading out the content of a secured device. The details on programming through the JTAG interface and programming specific JTAG instructions are given in the section “Programming via the JTAG Interface” on page 247. ATmega162(V/U/ ...
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... Bibliography ATmega162(V/U/L) 200 For more information about general Boundary-scan, the following literature can be consulted: • IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993 • Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison- Wesley, 1992 ...