ATMEGA162-16AC Atmel, ATMEGA162-16AC Datasheet - Page 247

• Manufacturer Part Number: ATMEGA162-16AC
• Description: IC MCU AVR 16K 5V 16MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

SPI Serial Programming
Characteristics
Programming via the
JTAG Interface
Programming Specific JTAG
Instructions
2513C–AVR–09/02
For characteristics of the SPI module, see “SPI Timing Characteristics” on page 264.
Programming through the JTAG interface requires control of the four JTAG specific
pins: TCK, TMS, TDI, and TDO. Control of the Reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The
device is default shipped with the Fuse programmed. In addition, the JTD bit in
MCUCSR must be cleared. Alternatively, if the JTD bit is set, the External Reset can be
forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins
are available for programming. This provides a means of using the JTAG pins as normal
port pins in running mode while still allowing In-System Programming via the JTAG
interface. Note that this technique can not be used when using the JTAG pins for
Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for
this purpose.
As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers.
The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG
instructions useful for Programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format.
The text describes which Data Register is selected as path between TDI and TDO for
each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can
also be used as an idle state between JTAG sequences. The state machine sequence
for changing the instruction word is shown in Figure 107.
ATmega162(V/U/L)
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