ATMEGA48V-10PI Atmel, ATMEGA48V-10PI Datasheet - Page 222
![IC AVR MCU 4K 5V 10MHZ 28-DIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATMEGA48V-10PI
Manufacturer Part Number
ATMEGA48V-10PI
Description
IC AVR MCU 4K 5V 10MHZ 28-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA48V-10PI
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA48V-12PI
ATMEGA48V-12PI
ATMEGA48V-12PI
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA48V-10PI
Manufacturer:
AGERE
Quantity:
85
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ATmega48/88/168
Figure 21-11. Data Transfer in Master Transmitter Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to trans-
mit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will
then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes
free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the
status code in TWSR will be 0x08 (see
transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit should be
cleared (by writing it to one) to continue the transfer. This is accomplished by writing the follow-
ing value to TWCR:
When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes
is detailed in
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is
done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not,
the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Regis-
ter. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the
transfer. This is accomplished by writing the following value to TWCR:
This scheme is repeated until the last byte has been sent and the transfer is ended by generat-
ing a STOP condition or a repeated START condition. A STOP condition is generated by writing
the following value to TWCR:
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR
value
TWCR
value
TWCR
value
TWCR
value
TWCR
value
SDA
SCL
Table
TWINT
TWINT
TWINT
TWINT
TWINT
1
1
1
1
1
21-2.
TRANSMITTER
Device 1
MASTER
TWEA
TWEA
TWEA
TWEA
TWEA
X
X
X
X
X
Device 2
RECEIVER
SLAVE
TWSTA
TWSTA
TWSTA
TWSTA
TWSTA
1
0
0
0
1
Table
Device 3
21-2). In order to enter MT mode, SLA+W must be
TWSTO
TWSTO
TWSTO
TWSTO
TWSTO
0
0
0
1
0
........
TWWC
TWWC
TWWC
TWWC
TWWC
Device n
X
X
X
X
X
V
CC
TWEN
TWEN
TWEN
TWEN
TWEN
1
1
1
1
1
R1
R2
–
0
–
0
–
0
–
0
–
0
2545S–AVR–07/10
TWIE
TWIE
TWIE
TWIE
TWIE
X
X
X
X
X
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