ATTINY2313-20SI Atmel, ATTINY2313-20SI Datasheet - Page 49

IC MCU AVR 2K FLASH 20SOIC

ATTINY2313-20SI

Manufacturer Part Number
ATTINY2313-20SI
Description
IC MCU AVR 2K FLASH 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheets

Specifications of ATTINY2313-20SI

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Other names
ATTINY2313-24SI
ATTINY2313-24SI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY2313-20SI
Manufacturer:
AT
Quantity:
95
Part Number:
ATTINY2313-20SI
Manufacturer:
RASTRONIC
Quantity:
20 000
2543L–AVR–08/10
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 24. Synchronization when Reading a Software Assigned Pin Value
INSTRUCTIONS
Figure
SYSTEM CLK
SYNC LATCH
24. The out instruction sets the “SYNC LATCH” signal at the positive edge of the
PINxn
r16
r17
out PORTx, r16
0x00
nop
t
pd
0xFF
in r17, PINx
0xFF
49

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