AT91SAM7S256-AU-001 Atmel, AT91SAM7S256-AU-001 Datasheet - Page 40

• Manufacturer Part Number: AT91SAM7S256-AU-001
• Description: IC ARM7 MCU 32BIT 256K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S256-AU-001

• Package / Case: 64-LQFP
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 55MHz
• Number Of I /o: 32
• Core Processor: ARM7
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Core Size: 16/32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: AT91SAM7S256AU001

10.10 PWM Controller
10.11 USB Device Port (Does not pertain to AT91SAM7S32/16)
10.12 Analog-to-digital Converter
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AT91SAM7S Series Summary
• Four channels, one 16-bit counter per channel
• Common clock generator, providing thirteen different clocks
• Independent channel programming
• USB V2.0 full-speed compliant, 12 Mbits per second.
• Embedded USB V2.0 full-speed transceiver
• Embedded 328-byte dual-port RAM for endpoints
• Four endpoints
• Suspend/resume logic
• 8-channel ADC
• 10-bit 384 K samples/sec. or 8-bit 583 Ksamples/sec. Successive Approximation Register
• ±2 LSB Integral Non Linearity, ±1 LSB Differential Non Linearity
• Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs
• External voltage reference for better accuracy on low voltage inputs
• Individual enable and disable of each channel
• Multiple trigger source
• Sleep Mode and conversion sequencer
• Four of eight analog inputs shared with digital signals
ADC
– One Modulo n counter providing eleven clocks
– Two independent linear dividers working on modulo n counter outputs
– Independent enable/disable commands
– Independent clock selection
– Independent period and duty cycle, with double buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Endpoint 0: 8 bytes
– Endpoint 1 and 2: 64 bytes ping-pong
– Endpoint 3: 64 bytes
– Ping-pong Mode (two memory banks) for isochronous and bulk endpoints
– Hardware or software trigger
– External trigger pin
– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
– Automatic wakeup on trigger and back to sleep mode after conversions of all
enabled channels
6175FS–ATARM–03-Dec-07