AT91M40800-33AI SL383 Atmel, AT91M40800-33AI SL383 Datasheet - Page 101
![IC ARM MCU 16BIT 100TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
AT91M40800-33AI SL383
Manufacturer Part Number
AT91M40800-33AI SL383
Description
IC ARM MCU 16BIT 100TQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91M40800-33AU.pdf
(18 pages)
2.AT91R40807-33AI.pdf
(153 pages)
3.AT91M40800-33AI.pdf
(21 pages)
Specifications of AT91M40800-33AI SL383
Core Processor
ARM7
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
AT91M4080033AISL3
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Receiver
Asynchronous Receiver
Figure 38. Asynchronous Mode: Start Bit Detection
Figure 39. Asynchronous Mode: Character Reception
1354D–ATARM–08/02
Rate Clock
16 x Baud
Sampling
Example: 8-bit, parity enabled 1 stop
Sampling
RXD
RXD
periods
0.5 bit
True Start Detection
The USART is configured for asynchronous operation when SYNC = 0 (bit 7 of
US_MR). In Asynchronous Mode, the USART detects the start of a received character
by sampling the RXD signal until it detects a valid start bit. A low level (space) on RXD is
interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling
clock, which is 16 times the baud rate. Hence a space which is longer than 7/16 of the
bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter
is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the RXD at the theoreti-
cal mid-point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock
(one bit period) so the sampling point is 8 cycles (0.5 bit periods) after the start of the bit.
The first sampling point is therefore 24 cycles (1.5 bit periods) after the falling edge of
the start bit was detected. Each subsequent bit is sampled 16 cycles (1 bit period) after
the previous one.
period
1 bit
D0
D1
True Start
Detection
D2
D3
D4
D5
D6
D7
Parity Bit
AT91X40 Series
Stop Bit
D0
101
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