DSPIC30F4013T-20I/ML Microchip Technology, DSPIC30F4013T-20I/ML Datasheet - Page 21

• Manufacturer Part Number: DSPIC30F4013T-20I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4013T20IM

39. Page 21-9, Register 21-1 I2CCON
Register 21-1:
40. I
TABLE 2:
 2004 Microchip Technology Inc.
IFS0<14>
IFS0<13>
IEC0<14>
IEC0<13>
IPC3<10:8>
IPC3<6:4>
Upper Byte:
bit 15
bit 5
Bit Location
I2CEN
R/W-0
in SFR
On page 21-9, Register 21-1: I2CCON: I
Register, the description of the ACKDT bit should
be corrected as follows. All other bit definitions do
not change and hence are not described.
Table 2 below, shows changes to the nomencla-
ture of the I
flag and priority bits. These changes should be
applied to the entire document.
2
C Interrupt Bit Names
Lower Byte:
bit 7
ACKDT: Acknowledge Data bit (When operating as I
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during acknowledge
0 = Send ACK during acknowledge
Legend:
R = Readable
W = Writable
HC = Cleared by Hardware
‘1’ = Bit is set at POR
GCEN
R/W-0
2
U-0
I2CCON: I
C module’s interrupt enable, status
INTERRUPT CONTROLLER
REGISTER MAP: I
NAMES
—
BCLIP<2:0>
I2CIP<2:0>
(Incorrect)
Bit Name
BCLIE
BCLIF
I2CIE
I2CIF
I2CSIDL
2
STREN
R/W-0
R/W-0
C Control Register
(Please read as)
MI2CIP<2:0>
SI2CIP<2:0>
Bit Name
2
MI2CIF
MI2CIE
C BIT
SI2CIF
SI2CIE
SCLREL
dsPIC30F Family Reference Manual
ACKDT
R/W-1
R/W-0
2
HC
C Control
C = Clearable bit
HS = Set by Hardware
‘0’ = Bit cleared at POR
IPMIEN
ACKEN
R/W-0
R/W-0
HC
2
C Master. Applicable during master receive.)
R/W-0
R/W-0
RCEN
A10M
HC
U = Unimplemented bit, read as ‘0’
S = Settable bit
x = Bit is unknown at POR
DISSLW
R/W-0
R/W-0
PEN
HC
R/W-0
SMEN
R/W-0
RSEN
HC
bit 8
DS80169E-page 21
R/W-0
SEN
HC
bit 0