DSPIC30F4013T-20I/ML Microchip Technology, DSPIC30F4013T-20I/ML Datasheet - Page 30

• Manufacturer Part Number: DSPIC30F4013T-20I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4013T20IM

dsPIC30F Family Reference Manual
46. Page 16-7, Section 16.2 DFLTCON
Register 16-1:
DS80169E-page 30
Upper Half:
bit 15
bit 15-11
bit 10-9
bit 8
bit 7
bit 6-4
bit 3-0
U-0
The control bits used to control the QEI digital input
filters may differ depending upon the device variant
that is used. This affects the control bits found in the
DFLTCON register. Please refer to the specific
device data sheet to determine which DFLTCON
control bits are implemented for the device you are
using. Some devices have two sets of control bits to
control the digital input filters. One set of control bits
sets the digital filter characteristics for the INDX pin.
—
Page 16-8, Section 16.3 Programmable
Digital Noise Filters
Page 16-14, Section 16.5.3.2 Index Pulse
De-skew
Unimplemented: Read as ‘0’
IMV<1:0>: Index Match Value – These bits allow the user to specify the state of the QEA and QEB input
CEID: Count Error Interrupt Disable
QEOUT: QEA/QEB/INDX pin Digital Filter Output Enable
QECK<2:0>: QEA/QEB/INDX Digital Filter Clock Divide Select Bits
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
y = Value set from configuration bits on POR or BOR
U-0
Lower Half:
bit 7
—
DFLTCON: Digital Filter Control Register
pins during an Index pulse when the POSCNT register is to be reset.
In 4X Quadrature Count Mode:
IMV1= Required State of Phase B input signal for match on index pulse
IMV0= Required State of Phase A input signal for match on index pulse
In 2X Quadrature Count Mode:
IMV1= Selects Phase input signal for Index state match (0 = Phase A, 1 = Phase B)
IMV0= Required State of the selected Phase input signal for match on index pulse
1 = Interrupts due to count errors are disabled
0 = Interrupts due to count errors are enabled
1 = Digital filter outputs enabled
0 = Digital filter outputs disabled (normal pin operation)
111 = 1:256 Clock Divide
110 = 1:128 Clock Divide
101 = 1:64 Clock Divide
100 = 1:32 Clock Divide
011 = 1:16 Clock Divide
010 = 1:4 Clock Divide
001 = 1:2 Clock Divide
000 = 1:1 Clock Divide
QEOUT
R/W-0
U-0
—
QECK<2:0>
U-0
—
W = Writable bit
‘1’ = Bit is set
R/W-0
U-0
—
R/W-0
The second set of control bits sets the digital filter
characteristics for the QEA and QEB pins. The
DS70063B
DFLTCON control register for these device variants.
Other device variants have one set of control bits
that set the digital filter characteristics for the INDX,
QEA and QEB pins. The DFLTCON register for
these device variants is provided in Register 16-1
below. If the device variant has this DFLTCON
register, then paragraph 5 of Section 16.3
“Programmable Digital Noise Filters” is not applica-
ble. Also, Section 16.5.3.2. “Index Pulse De-skew”
is not applicable.
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
IMV<1:0>
U-0
—
R/W-0
document
U-0
—
 2004 Microchip Technology Inc.
R/W-0
CEID
x = Bit is unknown
correctly
bit 8
U-0
—
depicts
U-0
—
bit 0
the