AT89C5131A-TISIL Atmel, AT89C5131A-TISIL Datasheet - Page 145

• Manufacturer Part Number: AT89C5131A-TISIL
• Description: IC 8051 MCU FLASH 32K USB 28SOIC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-TISIL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

4338F–USB–08/07
Table 103. UEPINT Register
UEPINT (S:F8h read-only)
USB Endpoint Interrupt Register
Reset Value = 00h
Bit Number
7
-
7
6
5
4
3
2
1
0
Mnemonic Description
EP6INT
EP6INT
EP5INT
EP4INT
EP3INT
EP2INT
EP1INT
EP0INT
Bit
6
-
Reserved
The value read from this bit is always 0. Do not set this bit.
Endpoint 6 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 6. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP6IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 5 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 5. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP5IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 4 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 4. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP4IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 3 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 3. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP3IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 2 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 2. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 1 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 1. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 0 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 0. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
EP5INT
5
EP4INT
4
EP3INT
3
EP2INT
2
EP1INT
1
EP0INT
0
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