AT89C5131A-TISIL Atmel, AT89C5131A-TISIL Datasheet - Page 66
![IC 8051 MCU FLASH 32K USB 28SOIC](/photos/6/82/68295/453-28-soic_sml.jpg)
AT89C5131A-TISIL
Manufacturer Part Number
AT89C5131A-TISIL
Description
IC 8051 MCU FLASH 32K USB 28SOIC
Manufacturer
Atmel
Series
AT89C513xr
Specifications of AT89C5131A-TISIL
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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Serial I/O Port
Framing Error Detection
66
AT89C5131A-L
The serial I/O port in the AT89C5131A-L is compatible with the serial I/O port in the
80C52.
It provides both synchronous and asynchronous communication modes. It operates as
an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex
modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simul-
taneously and at different baud rates.
Serial I/O port includes the following enhancements:
•
•
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-
ter (see Figure 34).
Figure 34. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Table 56) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 35 and Figure 36).
Figure 35. UART Timings in Mode 1
Framing error detection
Automatic address recognition
SMOD0 = X
SMOD0 = 1
RXD
SM0/FE
FE
RI
SMOD1
SMOD0
SM1
Start
Bit
D0
SM2
-
D1
REN
Set FE Bit if Stop Bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART Mode Control (SMOD0 = 0)
POF
To UART Framing Error Control
D2
TB8
GF1
D3
Data Byte
RB8
GF0
D4
D5
PD
TI
D6
IDL
RI
D7
SCON (98h)
PCON (87h)
Stop
Bit
4338F–USB–08/07
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